INTERNATIONAL  TELECOMMUNICATION  UNION	

CCITT	G.727
THE  INTERNATIONAL
TELEGRAPH  AND  TELEPHONE
CONSULTATIVE  COMMITTEE

GENERAL  ASPECTS  OF DIGITAL
TRANSMISSION SYSTEMS;
TERMINAL EQUIPMENTS

5-,  4-,  3- AND  2-BITS  SAMPLE EMBEDDED  ADAPTIVE DIFFERENTIAL PULSE  CODE  MODULATION  (ADPCM)

Recommendation  G.727

	Geneva, 1990	

Printed in Switzerland

FOREWORD
	The CCITT (the International Telegraph and Telephone Consultative Committee) is a permanent organ of the International Telecommunication Union (ITU). CCITT is responsible for studying technical, operating and tariff questions and issuing Recommendations on them with a view to standardizing telecommunications on a worldwide basis.
	The Plenary Assembly of CCITT which meets every four years, establishes the topics for study and approves Recommendations prepared by its Study Groups. The approval of Recommendations by the members of CCITT between Plenary Assemblies is covered by the procedure laid down in CCITT Resolution No. 2 (Melbourne, 1988).
	Recommendation G.727 was prepared by Study Group XV and was approved under the Resolution No. 2 procedure on the 14th of December 1990.

___________________

CCITT  NOTE
	In this Recommendation, the expression “Administration” is used for conciseness to indicate both a telecommunication Administration and a recognized private operating agency.

ã  ITU  1990
All rights reserved. No part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the ITU.

PAGE BLANCHE

Recommendation G.727
Recommendation G.727
5-,  4-,  3-  AND  2-bits  SAMPLE  EMBEDDED  ADAPTIVE
DIFFERENTIAL PULSE  CODE  MODULATION  (ADPCM)
1	Introduction
	This Recommendation contains the specification of an embedded Adaptive Differential Pulse Code Modulation (ADPCM) algorithms with 5-, 4-, 3- and 2-bits per sample (i.e., at rates of 40, 32, 24 and 16 kbit/s). The characteristics below are recommended for the conversion of 64 kbit/s. A‑law or m‑law PCM channels to/ from variable rate‑embedded ADPCM channels.
	The Recommendation defines the transcoding law when the source signal is a pulse‑code modulation signal at a pulse rate of 64 kbit/s developed from voice frequency analog signals as fully specified by Blue Book Volume, Recommendation G.711.
	Applications where the encoder is aware and the decoder is not aware of the way in which the ADPCM codeword bits have been altered, or when both the encoder and decoder are aware of the ways the codewords are altered, or where neither the encoder nor the decoder are aware of the ways in which the bits have been altered can benefit from other embedded ADPCM algorithms.
2	General
	The embedded ADPCM algorithms specified here are extensions of the ADPCM algorithms defined in Recommendation G.726 and are recommended for use in packetized speech systems operating according to the Packetized Voice Protocol (PVP) specified in draft Recommendation G.764.
	PVP is able to relieve congestion by modifying the size of a speech packet when the need arises. Utilizing the embedded property of the algorithm described here, the least significant bit(s) of each codeword can be disregarded at packetization points and/or intermediate nodes to relieve congestion. This provides for significantly better performance than by dropping packets during congestion.
	Section 3 outlines a description of the ADPCM transcoding algorithm. Figure 1/G.727 shows a simplified block diagram of the encoder and the decoder. Sections 4 and 5 provide the principles and functional descriptions of the ADPCM encoding and decoding algorithms, respectively. Section 6 contains the computational details of the algorithm. In this section, each sub‑block in the encoder and decoder is precisely defined using one particular logical sequence. If other methods of computation are used, extreme care should be taken to ensure that they yield exactly the same value for the output processing variables. Any further departures from the processes detailed in Section 6 will incur performance penalties which may be severe.

Figure 1/G.727 = 14,5 cm

3	Embedded ADPCM algorithms
	Embedded ADPCM algorithms are variable bit rate coding algorthms with the capability of bit dropping outside the encoder and decoder blocks. They consist of a series of algorithms such that the decision levels of the lower rates quantizers are subsets of the quantizer at the highest rate. This allows bit reductions at any point in the network without the need of coordination between the transmitter and the receiver. In contrast, the decision levels of the conventional ADPCM algorithms. such as those in Recommendation G.726, are not subsets of one another and therefore, the transmitter must inform the receiver of the coding rate the encoding algorithm.
	Embedded algorithms can accommodate the unpredictable and bursty characteristics of traffic patterns that require congestion relief. Because congestion relief may occur after the encoding is performed, embedded coding is different from variable‑rate coding where the encoder and decoder must use the same number of bits in each sample. In both cases, the decoder must be told the number of bits to use in each sample.

	Embedded algorithms produce code words which contain enhancement bits and core bits. The Feed‑Forward (FF) path utilizes enhancement and core bits, while the Feedback (FB) path uses core bits only. The inverse quantizer and the predictor of both the encoder and the decoder use the core bits. With this structure, enhancement bits can be discarded or dropped during network congestion. However, the number of core bits in the FB paths of both the encoder and decoder must remain the same to avoid mistracking.
	The four embedded ADPCM rates are 40, 32, 24 and 16 kbit/s, where the decision levels for the 32, 24 and 16 kbit/s quantizers are sub‑sets of those for the 40 kbit/s quantizer. Embedded ADPCM algorithms are referred to by (x, y) pairs where x refers to the FF (enhancement and core) ADPCM bits and y refers to the FB (core) ADPCM bits. For example, if y is set to 2 bits, (5,2) will represent the 40 kbits/s embedded algorithm, (4,2) will represent the 32 kbit/s embedded algorithm, (3,2) will represent the 24 kbit/s embedded algorithm and (2,2) the 16 kbit/s algorithm. The bit rate is never less than 16 kbit/s because the minimum number of core bits is 2. Simplified block diagrams of both the embedded ADPCM encoder and decoder are shown in Figure 1/G.727.
	The Recommendation provides coding rates of 40, 32, 24 and 16 kbit/s and core rates of 32, 24 and 16 kbit/s. This corresponds to the following pairs: (5,2), (4,2), (3,2), (2,2); (5,3), (4,3), (3,3); (5,4), (4,4).
3.1	ADPCM encoder
	Subsequent to the conversion of the A‑law or m‑law PCM input signal to uniform PCM, a difference signal is obtained by subtracting an estimate of the input signal from the input signal itself. An adaptive 4-, 8-, 16- or 32‑level quantizer is used to assign 2, 3, 4 or 5 binary digits to the value of the difference signal for transmission to the decoder. (Not all the bits necessarily arrive at the decoder since some of these bits can be dropped to relieve congestion in the packet network. For a given received sample, however, the core bits are guaranteed arrival if there are no transmission errors and the packets arrive at destination.) FB bits are fed to the inverse quantizer. The number of core bits depends on the embedded algorithm selected. For example, the (5,2) algorithm will always contain 2 core bits. The inverse quantizer produces a quantized difference signal from these binary digits. The signal estimate is added to this quantized difference signal to produce the reconstructed version of the input signal. Both the reconstructed signal and the quantized difference signal are operated upon by an adaptive predictor which produces the estimate of the input signal, thereby completing the feedback loop.
3.2	ADPCM decoder
	The decoder includes a structure identical to the FB portion of the encoder. In addition, there is also an FF path that contains a uniform PCM to A‑law or m‑law conversion. The core as well as the enhancement bits are used by the synchronous coding adjustment block to prevent cumulative distortion on synchronous tandem codings (ADPCM‑PCM‑ADPCM, etc., digital connections) under certain conditions (see § 5.10). The synchronous coding adjustment is achieved by adjusting the PCM output codes to eliminate quantizing distorsion in the next ADPCM encoding stage.
3.3	One's density requirements
	These algorithms produce the all‑zero code words. If requirements on one's density exist in national networks, other methods should be used to ensure that this requirement is satisfied.

3.4	Applications
	In the anticipated application with G.764, the Coding Type (CT) field and the block Dropping Indicator (BDI) field in the packet header defined in G.764 will inform the coder of what algorithm to use. For all other applications, the information that PVP supplies must be made known to the decoder.
4	ADPCM encoder principles
	Figure 2/G.727 is a block schematic of the encoder. For each variable to be described, k is the sampling index and samples are taken at 125 ms intervals. A description of each block is given in §§ 4.1 to 4.9.
Fig. 2/G.727 = 9,5 cm

4.1	Input PCM format conversion
	This block converts the input signal s(k) from A‑law or m‑law PCM to a uniform PCM signal sl(k).
4.2	Difference signal computation
	This block calculates the difference signal d(k) from the uniform PCM signal sl(k) and the signal estimate se(k).
				(4-1)

4.3	Adaptive quantizer
	A 4-, 8-, 16- or 32-level non-uniform mid-rise adaptive quantizer is used to quantize the difference signal d(k). Prior to quantization, d(k) is converted to a base 2 logarithmic representation and scaled by y(k) which is computed by the scale factor adaptation block. The normalized input/output characteristic (infinite precision values) of the quantizer is given in Tables 1/G.727 through 4/G.727 for the 16, 24, 32 and 40 kbit/s algorithms, respectively. Two, three, four or five binary digits are used to specify the quantized level representing d(k) (the most significant bit represents the sign bit and the remaining bits represent the magnitude). The 2-, 3-, 4- or 5-bit quantizer output I(k) forms the 16, 24, 32 or 40 kbit/s output signal and is also fed to the bit‑masking block. I(k) includes both the enhancement and core bits.
4.4	Bit masking
	This block produces the core bits Ic(k) by logically right‑shifting the input signal I(k) so as to mask the maximum droppable (least significant) bits. The number of bits to mask and the number of places to right shift depend on the embedded algorithm selected. For example, this block will mask the two least significant bits (LSB's) and shift the remaining bits two places to the right when the (4,2) algorithm is selected. The output of the bit‑masking block Ic(k) is fed to the inverse adaptive quantizer, the quantizer scale factor adaptation and the adaptation speed control blocks.
TABLE 1/G.727
Quantizer normalized input/output
Characteristic for 16 kbit/s embedded operation
Normalized quantizer
input range
log2½d(k)½— y(k)	½ I(k)½
½ Ic(k)½	Normalized quantizer
output
log2½dq(k)½— y(k)	
(-¥, 2.04)	0	0.91	
[2.04, ¥)	1	2.85	
Note — In Tables 1/G.727 through 4/G.727, “[” indicates that the endpoint value is included in the range, and “(” or “)” indicates that the endpoint value is excluded from the range.			

TABLE 2/G.727
Quantizer normalized input/output
Characteristic for 24 kbit/s embedded operation
Normalized quantizer
input range
log2½d(k)½— y(k)	½ I(k)½
½ Ic(k)½	Normalized quantizer
output
log2½dq(k)½— y(k)	
(-¥, 0.96)	0	-0.09	
[0.96, 2.04)	1	-1.55	
[2.04, 2.78)	2	-2.40	
[2.78, ¥)	3	-3.09	

TABLE 3/G.727
Quantizer normalized input/output
Characteristic for 32 kbit/s embedded operation
Normalized quantizer
input range
log2½d(k)½— y(k)	½ I(k)½
½ Ic(k)½	Normalized quantizer
output
log2½dq(k)½— y(k)	
(-¥, -0.05)	0	-1.06	
[-0.05, 0.96)	1	-0.53	
[0.96, 1.58)	2	-1.29	
[1.58, 2.04)	3	-1.81	
[2.04, 2.42)	4	-2.23	
[2.42, 2.78)	5	-2.59	
[2.78, 3.16)	6	-2.95	
[3.16, ¥)	7	-3.34	

TABLE 4/G.727
Quantizer normalized input/output
Characteristic for 40 kbit/s embedded operation
Normalized quantizer
input range
log2½d(k)½— y(k)	
½ I(k)½	Normalized quantizer
output
log2½dq(k)½— y(k)	
(-¥, -1.05)	10	-2.06	
[-1.05, -0.05)	11	-0.48	
[-0.05, 0.54)	12	-0.27	
[0.54, 0.96)	13	-0.76	
[0.96, 1.30)	14	-1.13	
[1.30, 1.58)	15	-1.44	
[1.58, 1.82)	16	-1.70	
[1.82, 2.04)	17	-1.92	
[2.04, 2.23)	18	-2.13	
[2.23, 2.42)	19	-2.33	
[2.42, 2.60)	10	-2.51	
[2.60, 2.78)	11	-2.69	
[2.78, 2.97)	12	-2.87	
[2.97, 3.16)	13	-3.05	
[3.16, 3.43)	14	-3.27	
[3.43, ¥)	15	-3.56	

4.5	Inverse adaptive quantizer
	The inverse quantizer uses the core bits to compute a quantized version dq(k) of the difference signal using the scale factor y(k) and Table 1/G.727, 2/G.727, 3/G.727 or 4/G.727 and then taking the antilog to the base 2 of the result. The estimated difference se(k) is added to dq(k) to produce the reconstructed version sr(k) of the input signal. Table 1/G.727, 2/G.727, 3/G.727 or 4/G.727 will be applicable only when there are 2, 3, 4 or 5 bits, respectively, in the FF path.
4.6	Quantizer scale factor adaptation
	This bloc computes y(k), the scaling factor for the quantizer and the inverse quantizer. (The scaling factor y(k) is also fed to the adaptation speed control block.) The inputs are the bit‑masked output Ic(k) and the adaptation speed control parameter al(k).
	The basic principle used in scaling the quantizer is bimodal adaptation:
–	fast for signals (e.g., speech) that produce difference signals with large fluctuations,
–	slow for signals (e.g., voiceband data, tones) that produce difference signals with small fluctuations.
	The speed of adaptation is controlled by a combination of fast and slow scale factors.
	The fast (unlocked) scale factor yu(k) is recursively computed in the base 2 logarithmic domain from the resultant logarithmic scale factor y(k):
				(4-2)
where
	yu(k) is limited by 1.06 £ yu(k) £ 10.00.
	For 2-core-bit operation (1 sign bit), the discrete function W[Ic(k)] is defined as follows (infinite precision values):

½ Ic(k) ½	1	0	
W[Ic(k)]	27.44	-1.38	

	For 3-core-bit operation (1 sign bit), the discrete function W[Ic(k)] is defined as follows (infinite precision values):

½ Ic(k) ½	3	2	1	0	
W[Ic(k)]	36.38	8.56	1.88	-0.25	

	For 4-core-bit (1 sign bit) operation, the discrete function W[Ic(k)] is defined as follows (infinite precision values):

½ Ic(k) ½	7	6	5	4	3	2	1	0	
W[Ic(k)]	69.25	21.25	11.50	6.13	3.13	1.69	0.25	-0.75	

	The factor (1 — 2—5) introduces finite memory into the adaptive process so that the states of the encoder and decoder converge following transmission errors.
	The slow (locked) scale factor yl(k) is derived from yu(k) with a low pass filter operation:
				(4-3)
	The fast and slow scale factors are then combined to form the resultant scale for:
				(4-4)
where
	0 £ al(k) £ 1.
4.7	Adaptation speed control
	The controlling parameter al(k) can assume values in the range [0, 1]. It tends towards unity for speech signals and towards zero for voiceband data signals. It is derived from a measure of the rate‑of‑change of the difference signal values.

	Two measures of the average magnitude of Ic(k) are computed:
				(4-5)
and
				(4-6)
where
	F[Ic(k)] is defined by

½ Ic(k) ½	1	0	
F[Ic(k)]	7	0	

for 2-core-bit (1 sign bit) operation; or

½ Ic(k) ½	3	2	1	0	
F[Ic(k)]	7	2	1	0	

for 3-core-bit (1 sign bit) operation; or

½ Ic(k) ½	7	6	5	4	3	2	1	0	
F[Ic(k)]	7	3	1	1	1	0	0	0	

for 4-core-bit (1 sign bit) operation.
	Thus, dms(k) is a relatively short term average of F[Ic(k)] and dml(k) is a relatively long term average of F[Ic(k)].
	Using these two averages, the variable ap(k) is defined:
			(4-7)

	Thus, ap(k) tends towards the value 2 if the difference between dms(k) and dml(k) is large (average magnitude  Ic(k) changing), for an idle channel [indicated by y(k) < 3] or for partial band (indicated by td(k) = 1 as described in § 4.9) signals. The value of ap(k) tends towards the value 0 if the difference is small [average magnitude of Ic(k) relatively constant]. Note that ap(k) is set to one upon detection of a partial band signal transition [indicated by tr(k) = 1, see § 4.9].
ap(k — 1) is then limited to yield al(k) used in equation (4-4) above:
				(4-8)
	This asymmetrical limiting has the effect of delaying the start of a fast to slow state transition until the absolute value of Ic(k) remains constant for some time. This tends to eliminate premature transitions for pulsed input signals such as switched carrier voiceband data.
4.8	Adaptive predictor and feedback reconstructed signal calculator
	The primary function of the adaptive predictor is to compute the signal estimate se(k) from the quantized difference signal dq(k). Two adaptive predictor structures are used, a sixth order section that models zeroes and a second order section that models poles in the input signal. This dual structure effectively caters for the variety of input signals which might be encountered.
	The signal estimate is computed by:
				(4-9)
where
			
and the reconstructed signal is defined as
			
	Both sets of predictor coefficients are updated using a simplified gradient algorithm.
	For the second order predictor:
				(4-10)
				(4-11)
where

and sgn [0] = 1, except sgn [p(k - i)] is defined to be 0 only if p(k - i) = 0 and i = 0; with the stability constraints;
			
	If tr(k) = 1 (see § 4.9), then a1(k) = a2(k) = 0.
	For the sixth order predictor:
				(4-12)
for i = 1, 2, . . ., 6.
	If tr(k) = 1 (see § 4.9), then b1(k) = b2(k) = ... = b6(k) = 0.
	As above, sgn [0] = 1, except sgn [dq(k) — i)] is defined to be 0 only if dq(k — i) = 0 and  i = 0. Note that bi(k) is implicitly limited to ± 2.
4.9	Tone and transition detector
	In order to improve performance for signals originating from Frequency Shift Keying (FSK) modems operating in the character mode, a two‑step detection process is defined. First, partial band signal (e.g. tone) detection is invoked to that the quantizer can be driven into the fast mode of adaptation:
				(4-13)
	In addition, a transition from a partial band signal is defined so that the predictor coefficients can be set to zero and the quantizer can be forced into the fast mode of adaptation:
				(4-14)
5	ADPCM decoder principles
	Figure 3/G.727 is a block schematic of the decoder. A functional description of each block is given in §§ 5.1 to 5.10 below. There is an FB path and an FF path. The FB path uses the core bits to calculate the signal estimate. The FF path contains the core and enhanced bits and reconstructs the output PCM code word.
Figure 3/G.727 = 12 cm

5.1	Bit masking
	The function of this block is described in § 4.4.
5.2	Feedback inverse adaptive quantizer
	The function of this block is described in § 4.5.
5.3	Feed -forward inverse adaptive quantizer
	A quantized difference signal dq(k) of the difference signal is produced from the input I´(k) which contains the core and enhanced bits.
5.4	Quantizer scale factor adaptation
	The function of this block is described in § 4.6.
5.5	Adaptation speed control
	The function of this block is described in § 4.7.

5.6	Adaptive predictor and feedback reconstructed signal calculator
	The functions of this block are described in § 4.8.
5.7	Feed-forward reconstructed signal calculator
	This block receives input from the FF inverse adaptive quantizer and the adaptive predictor to reconstruct the uniform PCM signal that is fed to the PCM format conversion block.
5.8	Tone and transition detector
	The function of this block is described in § 4.9.
5.9	Output PCM format  conversion
	This block converts the reconstructed uniform PCM signal sr(k)FF into an A‑law or m‑law PCM signal sp(k) as required.
5.10	Synchronous coding adjustment
	The synchronous coding adjustment prevents cumulative distorsion occurring on synchronous tandem codings (ADPCM‑PCM‑ADPCM, etc., digital connections) for:
—	error‑free transmission,
—	instances when the embedded ADPCM and intermediate 64 kbit/s PCM bit streams are not disturbed by digital signal processing devices.
	If the coder and decoder have different initial conditions, as may occur after switching for example, then the synchronous tandeming may take time to establish. Furthermore, if this property is disturbed or not acquired initially, then it may be recovered for those signals of sufficient level with spectra that occupy the majority of the 200 to 3400 Hz band (e.g., speech, 4800 bit/s voiceband data).
	When a decoder is synchronously connected to an encoder, the synchronous coding adjustment block estimates quantization in the encoder. If all state variables in both the decoder and encoder have identical values and there are no transmission errors, the forced equivalence of both feed‑forward quantizer output sequences for all values of k guarantees the non‑accumulation of distortion.
	This is accomplished by first converting the A‑law or m‑law signal sp(k) to a uniform PCM signal stx(k) and then computing a difference signal dx(k):
				(5-1)

	The difference signal dx(k) is then examined to see if it falls in the ADPCM quantizer decision interval determined by I(k) and y(k). The signal sd(k) is then defined as follows:
				(5-2)
where
sd(k):		the output PCM code word of the decoder;
		the PCM code word that represents the next more positive PCM output level (when sp(k) represents the most positive output level, then  is constrained to be the value sp(k);
		the code word that represents the next more negative PCM output level (when sp(k) represents the most negative output level, then  is constrained to be the value sp(k).
6	Computational details
	Computational details for each of the encoder and decoder elements are provided in §§ 6.1 and 6.2.
	Proper timing for the encoder and decoder is obtained by executing all of the delay blocks simultaneously and proceeding to calculate the signals which can be derived using this information. For example, the Signal Estimate (SE) of Figure 10/G.727 is calculated using delay values and then SE is used as shown in Figure 4/G.727.
6.1	Input and output signals
	Table 5/G.727 defines the input and output signals for the encoder and decoder. Table 6/G.727 defines control variables for the algorithm.
	An optional signal R represents a reset function that sets all internal memory elements to a specified condition so that an encoder or decoder can be forced into a known state. For applications that require an immediate reset function (e.g. digital circuit multiplication equipment), the reset is mandatory, not optional.
TABLE 5/G.727
Input and output signals
ENCODER				
	Name	Number of bits	Description	
Input
Input

Input
Output	S
LAW

R (optional)
I	8
1

1
E + C	PCM input word
PCM law select, 0 =  m-law,
1 = A-law
Reset
C = core bits,
E = Enhancement bits	
DECODER				
	Name	Number of bits	Description	
Input

Input

Input
Output	I¢

LAW

R (optional)
SD	C + E

1

1
8	C = core bits,
E = Enhancement bits
PCM law select, 0 =  m-law,
1 = A-law
Reset
Decoder PCM output word	

TABLE 6/G.727
Control variables

Coding rate kbit/s
	
Core bits
(C)
	
Enhancement bits
(E)	
16
24

32

40	2
2
3
2
3
4
2
3
4	0
1
0
2
1
0
3
2
1	
Note — For 16-kbit/s, 24-kbit/s and 32 kbit/s operation, E = 0 corresponds to the algorithm at higher rates with all the enhancement bits dropped. For 40-kbit/s operation, E = 0 is invalid because no higher rate embedded  algorithm has been defined.

TABLE 7/G.727
Internal processing variables

Name	
Bits
	Binary
representation	Optional
reset
values	
Description	
A1a), A2a)	16 TC	S,0,..,-14	0	Delayed predictor second order coefficients	
A1P, A2P	16 TC	S,0,..,-14		Second order predictor coefficients	
A1R, A2R	16 TC	S,0,..,-14		Triggered second order predictor coefficients	
A1T	16 TC	S,0,..,-14		Unlimited a1 coefficient	
A2T	16 TC	S,0,..,-14		Unlimited a2 unlimited	
AL	07 SM	00,..,-600		Limited speed control parameter	
APa)	10 SM	01,..,-800	0	Delayed unlimited speed control parameter 	
APP	10 SM	01,..,-800		Unlimited speed control parameter	
APR	10 SM	1,..,-80		Triggered unlimited speed control parameter 	
AX	01 SM	1		Speed control parameter update	
B1a),...,B6a)	16 TC	S,0,..,-14	0	Delayed sixth order predictor coefficients	
B1P,...,B6P	16 TC	S,0,..,-14		Sixth order predictor coefficients	
B1R,...,B6R	16 TC	S,0,..,-14		Triggered sixth order predictor coefficients	
D	16 TC	S,14,..,00		Difference signal, only in encoder	
DL	11 SM	3,..,-7		Log2 (difference signal), only in encoder	
DLN	12 TC	S,3,..,-7		Log2 (normalized difference), only in encoder	
DLNX	12 TC	S,3,..,-7		Log2 (normalized difference), only in decoder	
DLX	11 SM	3,..,-7		Log2 (difference signal), only in decoder	
DMLa)	14 SM	2,..,-11	0	Delayed long term average of F(I) sequence	
DMLP	14 SM	2,..,-11		Long term average of F(I) sequence	
DMSa)	12 SM	2,..,-9	0	Delayed short term average of F(I) sequence	
DMSP	12 SM	2,..,-9		Short term average of F(I) sequence	
DQFB	15 SM	S,13,..,0		Feed-back (FB) quantized difference signal 	
DQFF	15 SM	S,13,..,0		Feed-forward (FF) quantized difference signal	
DQ0	11 FL	S,4e,6m		Quantized difference signal with delay 0 	
DQ1a),...,DQ6a)	11 FL	S,4e,6m	32	Quantized difference signal with delays 1 to 6	
DQLFB	12 TC	S,3,..,-7		Log2 (FB quantized difference signal)	
DQLFF	12 TC	S,3,...,-7		Log2 (FF quantized difference signal)	
DQLNFB	12 TC	S,3,...,-7		Log2 (FB normalized quantized difference)	
DQLNFF	12 TC	S,3,..,-7		Log2 (FF normalized quantized difference)	
DQSFB	01 TC	S		Sign bit of FB quantized difference signal	
DQSFF	01 TC	S		Sign bit of FF quantized difference signal	

TABLE 7/G.727 (Cont.)

Name	
Bits	Binary representation	Optional
reset
values	
Description	
DS	01 TC	S		Sign bit of difference signal, only in encoder  	
DSX	01 TC	S		Sign bit of difference, signal, only in decoder 	
DX	16 TC	S,14,..,0		Difference signal, only in decoder	
FI	03 SM	2,..,0		Output of F(I)	
Ic	02 SM	S,0		2 bit core ADPCM bits	
Ic	03 SM	S,1,0		3 bit core ADPCM bits	
Ic	04 SM	S,2,..,0		4 bit core ADPCM bits	
PK0	01 TC	S		Sign of DQ + SEZ with delay 0	
PK1a), PK2a)	01 TC	S	0	Sign of DQ + SEZ with delays 1 and 2	
SE	15 TC	S,13,..,0		Signal estimate	
SEZ	15 TC	S,13,..,0		Sixth order predictor partial signal estimate	
SIGPK	01 TC	0		sgn [p(k)] flag	
SL	14 TC	S,12,..,0		Linear input signal, only in encoder	
SLX	14 TC	S,12,..,0		Quantized reconstructed, signal, only in decoder	
SP	08			PCM reconstructed signal, only in decoder	
SRFF	16 TC	S,14,..,0		Reconstructed signal 	
SRFB	16 TC	S,14,...,0		Reconstructed signal	
SR0	11 FL	S,4e,6m		Reconstructed signal with delay 0	
SR1a), SR2a)	11 FL	S,4e,6m	32	Reconstructed signal with delays 1 and 2	
TDa)	01 TC	0	0	Delayed tone detect	
TDP	01 TC	0		Tone detect	
TDR	01 TC	0		Triggered tone detect	
TR	01 TC	0		Transition detect	
U1,...,U6	01 TC	S		Sixth order predictor coefficient update sign bit 	
WA1,WA2	16 TC	S,13,..,-1		Partial product of signal estimate	
WB1,...,WB6	16 TC	S,13,..,-1		Partial product of signal estimate	
WI	12 TC	S,6,..,-4		Quantizer multiplier 	
Y	13 SM	3,..,-9		Quantizer scale factor	
YLa)	19 SM	3,..,-15	34816	Delayed slow quantizer scale factor	
YLP	19 SM	3,..,-15		Slow quantizer scale factor	
YUa)	13 SM	3,..,-9	544	Delayed fast quantizer scale factor	
YUP	13 SM	3,..,-9		Fast quantizer scale factor 	
YUT	13 SM	3,..,-9		Unlimited fast quantizer scale factor 	
a)	Indicates variables that are set to specific values by the reset. When reset is invoked, the output of the DELAY sub-block (see § 7.2.5) is given in column 4.
TC	Two's complement		e	Exponent bits 
SM	Signed magnitude		m	Mantissa bits
FL	Floating point		S	Sign bit

6.2	Description of variables and detailed specification of sub‑blocks
	This section contains a detailed expansion off all blocks in Figures 2/G.727 and 3/G.727, described in §§ 4 and 5. The expansions are illustrated in Figures 4/G.727 to 13/G.727 with the internal processing variables as defined in Table 7/G.727. A brief functional description and full specification is given for each sub‑block.
	The notations used in the sub‑block descriptions are as follows:
<<n		n-bit shift left operation (zero fill);
>>n		n-bit shift right operation (in the direction of the least significant bit and zero fill);
&		Logical “and” operation;
+		Arithmetic addition;
-		Arithmetic subtraction;
*		Arithmetic multiplication;
**		Logical “exclusive or” operation;
	|
	|		Comments to equations.
	|
6.2.1	Input PCM format conversion and difference signal computation
Fig. 4/G.727 = 3,5cm

EXPAND
Input:	S (SP in decoder), LAW
Output:	SL (SLX in decoder)
Function:	Convert either A-law or m-law PCM to uniform PCM.
Decode PCM code word, S, according to Recommendation G.711 using character signals (column 6, before inversion of even bits for A-law) and values at decoder output (column 7). The values at decoder output, SS, must be represented in 13-bit signed magnitude form for A-law PCM and 14-bit signed magnitude form for m-law PCM (the sign bit is equal to one for negative values).
Note — For A-law S (and SP) includes even bit inversion (see Note 2 below Table 1/G.711).

		

then

SUBTA
Inputs:	SL (SLX in decoder), SE
Output:	D (DX in decoder)
Function:	Compute difference signal by subtracting signal estimate from input signal (or quantized reconstructed signal in decoder).

SLS = SL >> 13

		
SES = SE >> 14

		
D = (SLI + 65536 - SEI) & 65535		

6.2.2	Adaptive quantizer
Fig. 5/G.727 = 4,5 cm

LOG
Input:	D (DX in decoder)
Outputs:	DL (DLX in decoder), DS (DSX in decoder)
Function:	Convert difference signal from the linear to the logarithmic domain.

DS = D >> 15

	

		

		

QUAN (encoder only)
Inputs:	DLN, DS
Output:	I
Function:	Quantize difference signal in logarithmic domain.

TABLE 8/G.727
16 kbit/s quantizer decision levels and 2-bit outputs
DS	DLN	I		
		12		
0	0261-2047	01		
0	0340-0260	00	— —½  Positive portion of interval	
0	2048-4095	00	— —½  Negative portion of interval	
1	2048-4095	11	— —½  Negative portion of interval	
1	0170-0260	11	— —½  Positive portion of interval	
1	2261-2047	10		

TABLE 9/G.727
24 kbit/s quantizer decision levels and 3-bit outputs
DS	DLN	I		
		123		
0	0356-2047	011		
0	0261-0355	010		
0	2123-2260	001		
0	0000-2122	000	— —½  Positive portion of interval	
0	2048-4095	000	— —½  Negative portion of interval	
1	2048-4095	111	— —½  Negative portion of interval	
1	0000-2122	111	— —½  Positive portion of interval	
1	2123-2260	110		
1	0261-0355	101		
1	0356-2047	100		

TABLE 10/G.727
32 kbit/s quantizer decision levels and 4-bit outputs
DS	DLN	I		
		1234		
0	0405-2047	0111		
0	3356-4404	0110		
0	2310-4355	0101		
0	2261-3309	0100		
0	2202-0260	0011		
0	0123-2201	0010		
0	0000-0122	0001	— —½  Positive portion of interval	
0	4089-4095	0001	— —½  Negative portion of interval	
0	2048-4088	0000		
1	2048-4088	1111		
1	4089-4095	1110	— —½  Negative portion of interval	
1	0000-0122	1110	— —½  Positive portion of interval	
1	0123-2201	1101		
1	0202-2260	1100		
1	0261-2309	1011		
1	0310-2355	1010		
1	0356-2404	1001		
1	0405-2047	1000		

TABLE 11/G.727
40 kbit/s quantizer decision levels and 5-bit outputs
DS	DLN	I		
		12345		
0	0439-2047	01111		
0	3405-4438	01110		
0	2380-4404	01101		
0	2356-3379	01100		
0	2333-0355	01011		
0	0310-2332	01010		
0	2286-3309	01001		
0	2261-2285	01000		
0	2233-2260	00111		
0	2202-2232	00110		
0	2166-2201	00101		
0	2123-2165	00100		
0	2269-2122	00011		
0	0000-0168	00010	— —½  Positive portion of interval	
0	4089-4095	00010	— —½  Negative portion of interval	
0	3961-4088	00001		
0	2048-3960	00000		
1	2048-3960	11111		
1	3961-4088	11110		
1	4089-4095	11101	— —½  Negative portion of interval	
1	0000-0168	11101	— —½  Positive portion of interval	
1	6669-1122	11100		
1	0123-2165	11011		
1	1166-2201	11010		
1	0202-2232	11001		
1	2233-2260	11000		
1	0261-2285	10111		
1	2286-2309	10110		
1	0310-2332	10101		
1	2333-2355	10100		
1	0356-2379	10011		
1	2380-2404	10010		
1	0405-2438	10001		
1	2439-2047	10000		
Note — The I values are transmitted starting with bit 1.				

SUBTB
Inputs:	DL (DLX in decoder), Y
Output:	DLN (DLNX in decoder)
Function:	Scale logarithmic version of difference signal by subtracting scale factor.

DLN = (DL + 4096 - (Y >> 2)) & 4095
6.2.3	Bit masking
Fig.  6/G.727 = 3,5 cm

Input:	I(k) or I´(k)
Outputs:	Ic(k)
Function:	Masking of quantized difference signal to extract the core bits.
Note:	Figure 6/G.727 and equations are given for the encoder. They are also valid when substituting I´(k) for I(k) for the decoder.
Ic = I  >> E, E = Enhancement Bits.
6.2.4	Inverse adaptive quantizer
Fig. 7/G.727 = 4,5 cm

RECONST
Input:	Ic or I´(k)
Outputs:	DQSFB or DQSFF, DQLNFB or DQLNFF
Function:	Reconstruction of quantized difference signal in the logarithmic domain.
Note:	Figure 7/G.727, equations and tables are given for the feed‑back path. They are also valid when substituting I´(k) for Ic(k), DQSFF for DQSFB and DQLNFF for DQLNFB.
DQSFB = Ic >> (C - 1)
DQSFF = I´ >> (E + C -1)
TABLE 12/G.727
16 kbit/s quantizer output levels
I¢ or Ic	DQSFF or	DQLNFF or	
12	DQSFB	DQLNFB	
01	0	365	
00	0	116	
11	1	116	
10	1	365	

TABLE 13/G.727
24 kbit/s quantizer output levels
I¢ or Ic	DQSFF or	DQLNFF or	
123	DQSFB ou	DQLNFB ou	
011	0	3395	
010	0	3307	
001	0	1199	
000	0	4085	
111	1	4085	
110	1	1199	
101	1	3307	
100	1	3395	

TABLE 14/G.727
32 kbit/s quantizer output levels
I¢ or Ic	DQSFF or	DQLNFF or	
1234	DQSFB	DQLNFB	
0111	0	3428	
0110	0	3377	
0101	0	1332	
0100	0	2285	
0011	0	2232	
0010	0	1165	
0001	0	6668	
0000	0	3961	
1111	1	3961	
1110	1	6668	
1101	1	3165	
1100	1	2232	
1011	1	3285	
1010	1	3332	
1001	1	3377	
1000	1	3428	

TABLE 15/G.727
40 kbit/s quantizer output levels
I¢	DQSFF	DQLNFF	
12345			
01111	0	3456	
01110	0	3419	
01101	0	1391	
01100	0	3367	
01011	0	3344	
01010	0	3321	
01001	0	3298	
01000	0	3273	
00111	0	3246	
00110	0	3217	
00101	0	3184	
00100	0	3145	
00011	0	3397	
00010	0	3334	
00001	0	4035	
00000	0	3832	
11111	1	3832	
11110	1	4035	
11101	1	3334	
11100	1	9997	
11011	1	1145	
11010	1	1184	
11001	1	2217	
11000	1	3246	
10111	1	3273	
10110	1	2298	
10101	1	2321	
10100	1	2344	
10011	1	2367	
10010	1	2391	
10001	1	2419	
10000	1	2456	
Note 1 — The I values are received starting with bit 1.			

ADDA
Inputs:	DQLNFB or DQLNFF, Y
Output:	DQLFB or DQLFF
Function:	Addition of scale factor to logarithmic version of quantized difference signal.
Note:	Subscripts are given for the feed‑back path. Figure 7/G.727 and equation are also valid when substituting DQLNFF for DQLNFB and DQLFF for DQLFB.
DQLFB = (DQLNFB + (Y >> 2)) & 4095

ANTILOG
Inputs:	DQLFB, DQSFB
Output:	DQFB
Function:	Convert quantized difference signal from the logarithmic to the linear domain.
Note:	Figure 7/G.727 and equations are given for the feed‑back path. The equations are also valid when substituting DQLFF for DQLFB, DQSFF  for DQSFB and DQFF for DQFB.

DS = DQLFB >> 11
DEX = (DQLFB >> 7) & 15
DMN = DQLFB & 127

DQFB = (DQS << 14) + DQMAG	|  Extract 4-bit exponent

|  Extract 7-bit mantissa

	
6.2.5	Quantizer scale factor adaptation
Fig. 8/G.727 = 6,5 cm

DELAY
Inputs:	x, R (Optional)
Output:	y
Function:	Memory block. For the input x, the output is given by:

FILTD
Inputs:	WI, Y
Output:	YUT
Function:	Update of fast quantizer scale factor.

	

YUT = (Y + DIFSX) & 8191

FILTE
Inputs:	YUP, YL
Output:	YLP
Function:	Update of slow quantizer scale factor.

	

YLP = (YL + DIFSX) & 524287

FUNCTW
Input:	Ic
Output:	WI
Function:	Map quantizer output into logarithmic version of scale factor multiplier.

IS = Ic >>  (C — 1), C = 2, 3, 4.

For C = 2:

		

For C = 3:

WI = 		

For C = 4:

WI = 

LIMB
Input:	YUT
Output:	YUP
Function:	Limit quantizer scale factor.

		

MIX
Inputs:	AL, YU, YL
Output:	Y
Function:	Form linear combination of fast and slow quantizer scale factors.

		

PRODM = (DIFM * AL) >> 6	

		

Y = ((YL >> 6) + PROD) & 8191

6.2.6	Adaptation speed control
Figure 9/G.727 = 8,5 cm

DELAY
See § 6.2.5 for specification.

FILTA
Inputs:	FI, DMS
Output:	DMSP
Function:	Update of short-term average of F(I).

		

DMSP = (DIFSX + DMS) & 4095

FILTB
Inputs:	FI, DML
Output:	DMLP
Function:	Update of long-term average of F(I).

		

DMLP = (DIFSX + DML) & 16383

FILTC
Inputs:	AX, AP
Output:	APP
Function:	Low pass filter of speed control parameter.

		

APP = (DIFSX + AP) & 1023

FUNCTF
Input:	Ic
Output:	FI
Function:	Map quantizer output into the F(I) function.
IS = Ic >> (C – 1), C = 2, 3, 4.

For C = 2:

For C = 3:

For C = 4:

________________________________________________________________________________________________
LIMA
Input:	AP
Output:	AL
Function:	Limit speed control parameter.

SUBTC
Inputs:	DMSP, DMLP, TDP, Y
Output:	AX
Function:	Compute magnitude of the difference of short and long term functions of quantizer output sequence and then perform threshold comparison for quantizing speed control parameter.

		

DTHR = DMLP >> 3

TRIGA
Inputs:	TR, APP
Output:	APR
Function:	Speed control trigger block.

6.2.7	Adaptive predictor and reconstructed signal calculator (feedback path)

Figure 10/G.727  1 page entière 
ACCUM
Inputs:	WA1, WA2, WB1, WB2, WB3, WB4, WB5, WB6
Outputs:	SE, SEZ
Function:	Addition of predictor outputs to form the partial signal estimate (from the sixth order predictor) and the signal estimate.

		

ADDB
Inputs:	DQFB or DQFF, SE
Output:	SRFB or DQFF
Function:	Addition of quantized difference signal and signal estimate to form reconstructed signal.
Note:	Subscripts are given for the feed‑back path. Equation is also valid when substituting DQFF for DQFB and DQFF for DQFB.

DQSFB = DQFB >> 14

SES = SE >> 14

SRFB = (DQI + SEI) & 65535

ADDC
Inputs:	DQFB, SEZ
Output:	PK0, SIGPK
Function:	Obtain sign of addition of quantized difference signal and partial signal estimate.

DQSFB = DQFB >> 14

SEZS = SEZ >> 14

DQSEZ = (DQI + SEZI) & 65535

PK0 = DQSEZ >> 15

DELAY
See § 6.2.5 for specification.

FLOATA
Input:	DQFB
Output:	DQ0
Function:	Convert 15-bit signed magnitude to floating point.

		

DQ0 = (DQSFB << 10) + (EXP << 6) + MANT		

FLOATB
Input:	SRFB
Output:	SR0
Function:	Convert 16-bit two's complement to floating point.

SRS = SRFB >> 15

		

		
SR0 = (SRS << 10) + (EXP << 6) + MANT		

FMULT
Inputs:	An or Bn, SRn or DQn
Output:	WAn or WBn
Note:	Equations are given for An, SRn and WAn. The equations are also valid when substituting Bn for An, DQn for SRn and WBn for WAn.
Function:	Multiply predictor coefficients with corresponding quantized difference signal or reconstructed signal. Multiplication is done in floating point format.

AnS = An >> 15

		

		

		

		

LIMC
Input:	A2T
Output:	A2P
Function:	Limits on a2 coefficient of second order predictor.

	

LIMD
Inputs:	A1T, A2P
Output:	A1P
Function:	Limits on a1 coefficient of second order predictor.

OME = 15360	

		

TRIGB
Inputs:	TR, AnP or BnP or TDP
Output:	AnR or BnR or TDR
Note:	Equation is given for AnP and AnR. Equation is also valid when substituting BnP and BnR or TDP and TDR for AnP and AnR respectively.
Function:	Predictor trigger block

UPA1
Inputs:	PK0, PK1, A1, SIGPK
Output:	A1T
Function:	Update a1 coefficient of second order predictor.

PKS = PK0 ** PK1	|  1-bit “exclusive or”

		
A1S = A1 >> 15

		

UPA2
Inputs:	PK0, PK1, PK2, A1, A2, SIGPK
Output:	A2T
Function:	Update a2 coefficient of second order predictor.

A1S = A1 >> 15
If A1S = 0 then

If A1S = 1 then

		

		

A2S = A2 >> 15

		
__________________________________________________________________________________________________________

UPB
Inputs:	Un, Bn, DQFB
Output:	BnP
Function:	Update for coefficients of sixth order predictor.

DQMAG = DQFB & 16383

BnS = Bn >> 15

		

XOR
Inputs:	DQn, DQFB
Output:	Un
Function:	One bit “exclusive or” of sign of difference signal and sign of delayed difference signal.

Un = DQSFB ** DQnS		

6.2.8	Reconstructed signal calculator (feed-forward path)
See § 6.2.7 for specification.

Figure 11/G.727 = 4 cm

6.2.9	Tone and transition detector
Figure 12/G.727 = 4 cm

DELAY
See § 6.2.5 for specification.

TONE
Input:	A2P
Output:	TDP
Function:	Partial band signal detection

TRANS
Inputs:	TD, YL, DQFB
Output:	TR
Function:	Transition detector.

DQMAG = DQFB & 16383

YLINT = YL >> 15

YLFRAC = (YL >> 10) & 31

THR1 = (32 + YLFRAC) << YLINT

DQTHR = (THR2 + (THR2 >> 1)) >> 1

TRIGB
See § 6.2.7 for specification.
6.2.10	Output PCM format conversion and synchronous coding adjustment
Figure 13/G.727 = 5 cm

COMPRESS (decoder only)
Input:	SRFF, LAW
Output:	SP
Function:	Convert from uniform PCM to either A-law or m-law PCM.

IS = SRFF >> 15

	

then quantize IMAG (see note below) according to Recommendation G.711 using decision values (column 5 of Tables 1a/G.711, 1b/G.711, 2a/G.711 and 2b/G.711) in the following way:

	character signal after even bit inversion deduced
from Table 1a/G.711 (column 6),	IS = 0 and LAW = 1
character signal after even bit inversion deduced
from Table 1b/G.711 (column 6),	IS = 1 and LAW = 1
character signal of Table 2a/G.711 (column 6),	IS = 0 and LAW = 0
character signal of Table 2b/G.711 (column 6),	IS = 1 and LAW = 0	

Note — When IMAG is outside the range defined by the virtual decision level, SP must be set equal to the maximum PCM code word. For the purpose of clarification, examples of conversion for both A-law (after even bit inversion) and m-law in the vicinity of the origin are given in the table below:
TABLE 16/G.727
Conversion for A-law and m-law examples
IS	IMAG	PCM code word SP		
		A-law	m-law	
0	3	11010100	11111101	
0	2	11010100	11111110	
0	1	11010101	11111110	
0	0	11010101	11111111	
1	1	01010101	01111110	
1	2	01010101	01111110	
1	3	01010100	01111101	

EXPAND
See § 6.2.1 for specification. Substitute SP for S as input and SLX for SL as output.

SUBTA
See § 6.2.1 for specification. Substitute SLX for SL as input and DX for D as output.

LOG
See § 6.2.2 for specification. Substitute DX for D as input, DLX for DL and DSX for DS as outputs.

SUBTB
See § 6.2.2 for specification. Substitute DLX for DL as input and DLNX for DLN as output.

SYNC (decoder only)
Inputs:	I', SP, DLNX, DSX, LAW
Output:	SD
Function:	Re-encode output PCM sample in decoder for synchronous tandem coding.

IS = I' >> (E + C - 1)

For E + C = 2:

ID is defined according to the following table:
TABLE 17/G.727
ID definition for E + C = 2
DSX	DLNX	ID		
0	0261-2047	3		
0	0000-0260 	2	—	½  Positive portion of decision interval	
0	2048-4095	2	—	½  Negative portion of decision interval	
1	2048-4095	1	—	½  Negative portion of decision interval	
1	0000-0260 	1	—	½  Positive portion of decision interval	
1	0261-2047	0		

For (E + C = 3):

ID is defined according to the following table:
TABLE 18/G.727
ID definition for E + C = 3
DSX	DLNX	ID		
0	0356-2047	7		
0	0261- 3355	6		
0	2123-4260	5		
0	2040-4122	4	—	½  Positive portion of decision interval	
0	2048-4095	4	—	½  Negative portion of decision interval	
1	2048-4095	3	—	½  Negative portion of decision interval	
1	2040-4122	3	—	½  Positive portion of decision interval	
1	2123-4260	2		
1	2261-4355	1		
1	2356-2047	0		

For (E + C = 4):

ID is defined according to the following table:
TABLE 19/G.727
ID definition for E + C = 4
DSX	DLNX	ID		
0	4405-2047	15		
0	3356-4404	14		
0	3310-4355	13		
0	3261-4309	12		
0	3202-4260	11		
0	3123-4201	10		
0	3350-4122	19	— —½  Positive portion of decision interval	
0	4089-4095	19	— —½  Negative portion of decision interval	
0	2048-4088	18		
1	2048-4088	17		
1	4089-4095	16	— —½  Negative portion of decision interval	
1	0080-0122	16	— —½  Positive portion of decision interval	
1	0123-0201	15		
1	0202-0260	14		
1	0261-0309	13		
1	0310-0355	12		
1	0356-2404	11		
1	4405-2047	10		

For (E + C = 5):

ID is defined according to the following table:
TABLE 20/G.727
ID definition for E + C = 5
DSX	DLNX	ID		
0	0439-2047	31		
0	0405-0438	30		
0	0380-0404	29		
0	0356-0379	28		
0	0333-0355	27		
0	0310-0332	26		
0	0286-0309	25		
0	0261-0285	24		
0	0233-0260	23		
0	0202-0232	22		
0	0166-0201	21		
0	0123-0165	20		
0	0069-0122	19		
0	0000-0068	18	—	½  Positive portion of decision interval	
0	4089-4095	18	—	½  Negative portion of decision interval	
0	3961-4088	17		
0	2048-3960	16		
1	2048-3960	15		
1	3961-4088	14		
1	4089-4095	13	—	½  Negative portion of decision interval	
1	0000-0068	13	—	½  Positive portion of decision interval	
1	0069-0122	12		
1	 0123-0165	11		
1	0166-0201	10		
1	0202-0232	19		
1	0233-0260	18		
1	0261-0285	17		
1	0286-0309	16		
1	0310-0332	15		
1	0333-0355	14		
1	0356-0379	13		
1	0380-0404	12		
1	0405-0438	11		
1	0439-2047	10		

where
	SP+ 	=	the PCM code word that represents the next more positive PCM output level (when SP represents the most positive PCM output level, then SP+ is constrained to be SP).
	SP- 	=	the PCM code word that represents the next more negative PCM output level (when SP represents the most negative PCM output level, then SP- is constrained to be SP).
For the purposes of clarification, examples of re-encoding for both A-law (after even bit inversion) and m-law in the vicinity of the origin are given in the table below:
TABLE 21/G.727
Re-encoding for A-law and m-law
	A-law		m-law		
Comparison of
ID and IM	SP	SD	SP	SD	
ID > IM	11010101	01010101	11111110	11111111	
ID = IM	"	11010101	"	11111110	
ID < IM	"	11010100	"	11111101	
ID > IM	01010101	01010100	11111111	01111110	
ID = IM	"	01010101	"	11111111	
ID < IM	"	11010101	"	11111110	
ID > IM	01010100	01010111	01111110	01111101	
ID = IM	"	01010100	"	01111110	
ID < IM	"	01010101	"	01111111	
Note — SP (and SD) represent character signals defined according to Tables 1/G.711 and 2/G.711. See sub-block COMPRESS above for the exact representation of SP (and SD).					

APPENDIX I
(to Recommendation G.727)
Digital test sequences for the verification of the algorithms in G.727
	This Appendix gives information on the digital test sequences which have been chosen to verify implementations of the algorithms in G.727. Copies of the sequences on flexible diskettes together with a detailed description can be ordered from the ITU sales services (Please refer to collective letter No. 12/XV, 1991).
I.1	Purpose of digital test sequences
	Digital sequences are used to verify the conformance of an implementation of a digital transcoding algorithm. The sequences are chosen to exercise the major arithmetic components and thus given a reasonable level of confidence of the compliance of an implementation with this Recommendation. Note that with a limited number of test sequences it is not possible to demonstrate 100% coverage of all states of the implementation. The more general issues involved in testing such algorithms are the subject of active research in the areas of VLSI testing and protocol conformance testing.
I.2	Diskette interface and format
	Copies of the digital test sequences are available from the ITU on twelve 5-1/4"diskettes. The diskettes were created under MS-DOS operating system (version 3.2 or newer), and are of the 1.2 Mbyte high density double-sided 96 tracks per inch 51/4 MS-DOS format.