.rs .\" Troff code generated by TPS Convert from ITU Original Files .\" Not Copyright ( c) 1991 .\" .\" Assumes tbl, eqn, MS macros, and lots of luck. .TA 1c 2c 3c 4c 5c 6c 7c 8c .ds CH .ds CF .EQ delim @@ .EN .nr LL 40.5P .nr ll 40.5P .nr HM 3P .nr FM 6P .nr PO 4P .nr PD 9p .po 4P .rs \v | 5i' .sp 2P .LP \fBRecommendation\ O.151\fR \v'1P' .RT .sp 2P .ce 1000 \fBERROR\ PERFORMANCE\ MEASURING\ EQUIPMENT\ FOR\fR .EF '% Fascicle\ IV.4\ \(em\ Rec.\ O.151'' .OF '''Fascicle\ IV.4\ \(em\ Rec.\ O.151 %' .ce 0 .sp 1P .ce 1000 \fBDIGITAL\ SYSTEMS\ AT\ THE\ PRIMARY\ BIT\ RATE\ AND\ ABOVE\fR .FS This Recommendation is the joint responsibility of Study Groups\ IV, XVII and XVIII. .FE .ce 0 .sp 1P .ce 1000 \fI(Geneva, 1976; amended Geneva, 1980, Malaga\(hyTorremolinos, 1984\fR .sp 9p .RT .ce 0 .sp 1P .ce 1000 \fIand Melbourne, 1988)\fR \v'1P' .ce 0 .sp 1P .PP The requirements for the characteristics of bit\(hyerror performance measuring equipment which are described below must be adhered to in order to ensure compatibility between equipments standardized by the CCITT, and produced by different manufacturers. .sp 1P .RT .sp 2P .LP \fB1\fR \fBGeneral\fR .sp 1P .RT .PP The equipment is designed to measure the bit\(hyerror performance of digital transmission systems by the direct comparison of a pseudorandom test pattern with an identical locally generated test pattern. In addition the capability to measure errored time intervals is provided. .RT .sp 2P .LP \fB2\fR \fBTest patterns\fR .sp 1P .RT .sp 1P .LP 2.1 \fIPseudorandom pattern\fR \fIfor systems using a 2\fI \fIpattern length\fR .sp 9p .RT .PP This pattern is to be produced by means of a shift register incorporating appropriate feedback (see Figure\ 1/O.151 and Table\ 1/O.151): .RT .ad r Number of shift register stages \ \ 15 \v'4p' .ad b .RT .ad r Pattern length \ \ 2\u1\d\u5\d\ \(em\ 1\ =\ 32 | 67\ bits \v'4p' .ad b .RT .PP Feedback taken from the 14th and 15th stage via an exclusive\(hyOR\(hygate to the first stage .ad r Longest sequence of zeros \ \ 15 (inverted\ signal) .ad b .RT .sp 1P .LP 2.2 \fIPseudorandom pattern for systems using 2\fR \fI\fI \fIpattern length\fR .sp 9p .RT .PP This pattern is to be produced by means of a shift register incorporating appropriate feedback (see Figure\ 2/O.151): .RT .ad r Number of shift register stages \ \ 23 \v'4p' .ad b .RT .ad r Pattern length \ \ 2\u2\d\u3\d\ \(em\ 1\ =\ 8 | 88 | 07 bits \v'4p' .ad b .RT .PP Feedback taken from the 18th and 23rd stages via an exclusive\(hyOR\(hygate to the first stage .ad r Longest sequence of zeros \ \ 23 (inverted signal) \v'4p' .ad b .RT .LP .sp 6 .bp .LP .rs .sp 33P .ad r \fBTable\ 1/O.151 [T1.151], p.\fR .sp 1P .RT .ad b .RT .LP .rs .sp 15P .ad r \fBFigure\ 1/O.151, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 23P .ad r \fBFigure\ 2/O.151 p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 2.3 \fIPseudorandom pattern\fR \fIfor systems using 2\fI \fIpattern length\fR .sp 9p .RT .PP This pattern may be generated by a twenty stage shift register with feedback taken from the seventeenth and twentieth stages. The output signal is taken from the twentieth stage, and an output bit is forced to be a \*Qone\*U whenever the next 14\ bits are all \*Qzero\*U. .PP The quasi\(hyrandom sequence satisfies the following: \v'6p' .RT .sp 1P .ce 1000 \fIQ\fR\d\fIn\fR\\d+\u\fR\d1\u (\fIk\fR + 1) = \fIQ\fR\d\fIn\fR\u(\fIk\fR ), \fIn\fR = 1, 2, | | | ,\ 19, .ce 0 .sp 1P .ce 1000 \fIQ\fR\d1\u (\fIk\fR + 1) = \fIQ\fR\d1\\d7\u(\fIk\fR ) \o'\(ci+' \fIQ\fR\d2\\d0\u(\fIk\fR ), and .ce 0 .sp 1P .ce 1000 \fIRD\fR (\fIk\fR ) = \fIQ\fR\d2\\d0\u(\fIk\fR ) + \fIQ\fR\d6\u(\fIk\fR ) + . | | + \fIQ\fR\d1\\d9\u(\fIk\fR ) .ce 0 .sp 1P .LP .sp 1 where .LP \fIQ\fR\d\fIn\fR\u(\fIk\fR ) = Present state for \fIn\fR th stage .LP \fIQ\fR\d\fIn\fR\u(\fIk\fR + 1) = Next state for \fIn\fR th stage .LP \fIRD\fR (\fIk\fR ) = Present value of output .LP + = a logic OR operation .LP \o'\(ci+' = a logic EXCLUSIVE OR operation .LP (\ ) = a logic NEGATION operation. .sp 1P .LP 2.4 \fIFixed patterns (optional)\fR .sp 9p .RT .PP Fixed patterns of all ones and alternating ones and zeros may be provided. .bp .RT .sp 2P .LP \fB3\fR \fBBit rate\fR .sp 1P .RT .PP The bit rates in accordance with CCITT Recommendations are indicated in Table\ 2/O.151. .RT .ce \fBH.T. [T2.151]\fR .ce TABLE\ 2/O.151 .ce \fBBit rates, pertinent Recommendations and pseudo\fR .ce \fBrandom test patterns\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(30p) | cw(54p) | cw(72p) | cw(36p) | cw(36p) . Bit rates (kbit/s) { Recommendations corresponding to multiplex system } { Recommendations corresponding to digital line section/line system } Bit rate tolerance Test pattern _ .T& cw(30p) | cw(54p) | lw(72p) | cw(36p) | cw(36p) . \ \ 1 | 54 G.733 [1] { G.911 [8], G.951 [9], G.955 [10] } { \(+- 50 | (mu | 0\uD\dlF261\u6\d } { 2\u1\d\u5\d\(em1, 2\u2\d\u0\d\(em1 } _ .T& cw(30p) | cw(54p) | lw(72p) | cw(36p) | cw(36p) . \ \ 2 | 48 G.732 [2] { G.921 [11], G.952 [12], G.956 [13] } { \(+- 50 | (mu | 0\uD\dlF261\u6\d } 2\u1\d\u5\d\(em1 _ .T& cw(30p) | cw(54p) | lw(72p) | cw(36p) | cw(36p) . \ \ 6 | 12 G.743 [3] { G.912 [14], G.951 [9], G.955 [10] } { \(+- 30 | (mu | 0\uD\dlF261\u6\d } { 2\u1\d\u5\d\(em1, 2\u2\d\u0\d\(em1 } _ .T& cw(30p) | cw(54p) | lw(72p) | cw(36p) | cw(36p) . \ \ 8 | 48 G.742 [4], G.745 [5] { G.921 [11], G.952 [12], G.956 [13] } { \(+- 30 | (mu | 0\uD\dlF261\u6\d } 2\u1\d\u5\d\(em1 _ .T& cw(30p) | cw(54p) | lw(72p) | cw(36p) | cw(36p) . \ 32 | 64 G.752 [6] { G.913 [15], G.953 [16], G.955 [10] } { \(+- 10 | (mu | 0\uD\dlF261\u6\d } { 2\u1\d\u5\d\(em1, 2\u2\d\u0\d\(em1 } _ .T& cw(30p) | cw(54p) | lw(72p) | cw(36p) | cw(36p) . \ 34 | 68 G.751 [7] { G.921 [11], G.954 [17], G.956 [13] } { \(+- 20 | (mu | 0\uD\dlF261\u6\d } 2\u2\d\u3\d\(em1 _ .T& cw(30p) | cw(54p) | lw(72p) | cw(36p) | cw(36p) . \ 44 | 36 G.752 [6] { G.914 [18], G.953 [16], G.955 [10] } { \(+- 20 | (mu | 0\uD\dlF261\u6\d } { 2\u1\d\u5\d\(em1, 2\u2\d\u0\d\(em1 } _ .T& cw(30p) | cw(54p) | lw(72p) | cw(36p) | cw(36p) . 139 | 64 G.751 [7] { G.921 [11], G.954 [17], G.956 [13] } { \(+- 15 | (mu | 0\uD\dlF261\u6\d } 2\u2\d\u3\d\(em1 _ .TE .nr PS 9 .RT .ad r \fBTable 2/O.151 [T2.151], p.\fR .sp 1P .RT .ad b .RT .PP \fINote\fR \ \(em\ Normally only the appropriate combination of bit rates \(em\ either 2048\ kbit/s, 8448\ kbit/s,\ etc. or 1544\ kbit/s, 6312\ kbit/s,\ etc.\ \(em will be provided in a given instrumentation. .sp 2P .LP \fB4\fR \fBInterfaces\fR .sp 1P .RT .PP The interface characteristics (impedances, levels, codes, etc.) should be in accordance with Recommendation\ G.703\ [19]. .PP In addition to providing for terminated measurements the instrumentation shall also be capable of monitoring at protected test points on digital equipment. Therefore, a high impedance and/or additional gain should be provided to compensate for the loss at monitoring points already provided on some equipments. .RT .sp 2P .LP \fB5\fR \fBError\(hyratio measuring range\fR .sp 1P .RT .PP The receiving equipment of the instrumentation should be capable of measuring bit\(hyerror ratios in the range 10\uD\dlF261\u3\d to 10\uD\dlF261\u8\d. In addition, it should be possible to measure bit\(hyerror ratios of 10\uD\dlF261\u9\d and 10\uD\dlF261\u1\d\u0\d; this can be achieved by providing the capability to count cumulative errors. .RT .sp 2P .LP \fB6\fR \fBMode of operation\fR .sp 1P .RT .PP The mode of operation should be such that the signal to be tested is first converted into a unipolar (binary) signal in the error measuring instrument and subsequently the bit comparison is made also with a reference signal in binary form. .PP Facilities may \fIoptionally\fR | e provided to allow the direct comparison at line code (e.g.\ AMI or HDB\(hy3) with correspondingly coded reference signals. In the case of such measurements polarity distinction is possible, so that errors caused by the injection or omission of positive or negative pulses can be determined separately. .bp .RT .sp 2P .LP \fB7\fR \fBMeasurement of\fR \fBerrored time intervals\fR .sp 1P .RT .PP The instrument shall be capable of detecting errored seconds and other errored or error\(hyfree time intervals as defined in \(sc\ 1.4 of Recommendation\ G.821\ [20] and of deriving error performance reduced to 64\ kbit/s in accordance with Annex\ D to Recommendation\ G.821\ [20] .FS Error performance evaluation at bit rates other than 64\ kbit/s is under study. .FE . The number of errored or error\(hyfree time intervals in a selectable observation period from 1\ minute to 24\ hours, or continuous, shall be counted and displayed. .PP For this measurement the error detection circuits of the instrument shall be controlled by an internal timer which sets intervals of equal length and which operates independently of the occurrence of errors. .RT .sp 2P .LP \fB8\fR \fBOperating environment\fR .sp 1P .RT .PP The electrical performance requirements shall be met when operating at the climatic conditions as specified in Recommendation\ O.3, \(sc\ 2.1. .RT .sp 2P .LP \fBReferences\fR .sp 1P .RT .LP [1] CCITT Recommendation \fICharacteristics of primary PCM multiplex\fR \fIequipment operating at 1544\ kbit/s\fR , Vol.\ III, Rec.\ G.733. .LP [2] CCITT Recommendation \fICharacteristics of primary PCM multiplex\fR \fIequipment operating at 2048\ kbit/s\fR , Vol.\ III, Rec.\ G.732. .LP [3] CCITT Recommendation \fISecond\(hyorder digital multiplex equipment\fR \fIoperating at 6312\ kbit/s and using positive justification\fR , Vol.\ III, Rec.\ G.743. .LP [4] CCITT Recommendation \fISecond\(hyorder digital multiplex equipment\fR \fIoperating at 8448\ kbit/s and using positive justification\fR , Vol.\ III, Rec.\ G.742. .LP [5] CCITT Recommendation \fISecond\(hyorder digital multiplex equipment\fR \fIoperating at 8448\ kbit/s and using positive/zero/negative\fR \fIjustification\fR , Vol.\ III, Rec.\ G.745. .LP [6] CCITT Recommendation \fICharacteristics of digital multiplex\fR \fIequipments based on a second\(hyorder bit rate of 6312\ kbit/s\fR \fIand using positive justification\fR , Vol.\ III, Rec.\ G.752. .LP [7] CCITT Recommendation \fIDigital multiplex equipments operating\fR \fIat the third\(hyorder bit rate of 34 | 68\ kbit/s and the\fR \fIfourth\(hyorder bit rate of 139 | 64\ kbit/s and using\fR \fIpositive justification\fR , Vol.\ III, Rec.\ G.751. .LP [8] CCITT Recommendation \fIDigital line sections\fR \fIat 1544\ kbit/s\fR , Vol.\ III, Rec.\ G.911. .LP [9] CCITT Recommendation \fIDigital line systems based on the\fR \fI1544\ kbit/s hierarchy on symmetric pair cables,\fR Vol.\ III, Rec.\ G.951. .LP [10] CCITT Recommendation \fIDigital line systems based on the\fR \fI1544\ kbit/s hierarchy on optical fibre cables\fR , Vol.\ III, Rec.\ G.955. .LP [11] CCITT Recommendation \fIDigital sections based on the\fR \fI2048\ kbit/s hierarchy\fR , Vol.\ III, Rec.\ G.921. .LP [12] CCITT Recommendation \fIDigital line systems based on the\fR \fI2048\ kbit/s hierarchy on symmetric pair cables\fR , Vol.\ III, Rec.\ G.952. .LP [13] CCITT Recommendation \fIDigital line systems based on the\fR \fI2048\ kbit/s hierarchy on optical fibre cables\fR , Vol.\ III, Rec.\ G.956. .LP [14] CCITT Recommendation \fIDigital line sections at 6312\ kbit/s\fR , Vol.\ III, Rec.\ G.912. .LP [15] CCITT Recommendation \fIDigital line sections at 32 | 64\ kbit/s\fR , Vol.\ III, Rec.\ G.913. .LP [16] CCITT Recommendation \fIDigital line systems based on the\fR \fI1544\ kbit/s hierarchy on coaxial pair cables\fR , Vol.\ III, Rec.\ G.953. .LP [17] CCITT Recommendation \fIDigital line systems based on the\fR \fI2048\ kbit/s hierarchy on coaxial pair cables\fR , Vol.\ III, Rec.\ G.954. .LP [18] CCITT Recommendation \fIDigital line sections at 44 | 36\ kbit/s\fR , Vol.\ III, Rec.\ G.914. .LP [19] CCITT Recommendation \fIPhysical/electrical characteristics of\fR \fIhierarchical digital interfaces\fR , Vol.\ III, Rec.\ G.703. .LP [20] CCITT Recommendation \fIError performance on an international\fR \fIdigital connection forming part of an integrated services digital\fR \fInetwork\fR , Vol.\ III, Rec.\ G.821. .bp .sp 2P .LP \fBRecommendation\ O.152\fR .RT .sp 2P .sp 1P .ce 1000 \fBERROR\ PERFORMANCE\ MEASURING\ EQUIPMENT\ FOR\ 64\ kbit/s\ PATHS\fR .EF '% Fascicle\ IV.4\ \(em\ Rec.\ O.152'' .OF '''Fascicle\ IV.4\ \(em\ Rec.\ O.152 %' .ce 0 .sp 1P .ce 1000 \fI(Malaga\(hyTorremolinos, 1984; amended, Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .PP The requirements for the characteristics of a bit\(hyerror performance measuring equipment which are described below must be adhered to in order to ensure compatibility between equipments standardized by the CCITT, and produced by different manufacturers. .sp 1P .RT .sp 2P .LP \fB1\fR \fBGeneral\fR .sp 1P .RT .PP The set is designed to measure the bit\(hyerror performance of digital paths (operating at 64\ kbit/s) by the direct comparison of a pseudorandom test pattern with an identical locally generated test pattern. .RT .sp 2P .LP \fB2\fR \fBTest patterns\fR .sp 1P .RT .sp 1P .LP 2.1 \fIPseudorandom pattern\fR .sp 9p .RT .PP This pattern is to be produced by means of a shift register incorporating appropriate feedback (see Figure\ 1/O.152): .RT .ad r Number of shift register stages \ \ 11 \v'2p' .ad b .RT .ad r Pattern length \ \ 2\u1\d\u1\d \(em 1 = 2047 bits \v'2p' .ad b .RT .LP Feedback taken from the outputs of the 9th and 11th stage via an exclusive\(hyOR\(hygate to the first stage .ad r Longest sequence of zeros \ \ 10 (non\(hyinverted signal) \v'2p' .ad b .RT .PP \fINote\ 1\fR \ \(em\ In the case of international testing where the measurement includes systems based on 1544\ kbit/s it is necessary to modify the test sequence in such a way that more than seven consecutive \*Q0\*U\(hybits are avoided. This is achieved by forcing the output signal to \*Q1\*U whenever the next 7\ bits of the sequence are all zeros. .PP \fINote\ 2\fR \ \(em\ It is recommended to use the test pattern of 2047\ bit length also at other bit rates in the range 48\ kbit/s to 168\ kbit/s. .RT .LP .rs .sp 17P .ad r \fBFigure 1/O.152, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 2.2 \fIFixed patterns\fR | optional)\fR .sp 9p .RT .PP Fixed patterns of all ones (. | | | 111 | | | ) and alternating ones and zeros (. | | | 010 | | | ) may be provided. .RT .sp 2P .LP \fB3\fR \fBBit rate\fR .sp 1P .RT .PP Bit rate in accordance with CCITT Recommendations\ G.703, \(sc\ 1\ [1] and V.36\ [2] of 64\ kbit/s: .RT .LP a) bit rate tolerance (Recommendation G.703 [1]): \(+- | 00 | (mu | 0\uD\dlF261\u6\d, .LP b) bit rate tolerance (Recommendation V.36 [2]), optional: \(+- | 0\ \(mu\ 10\uD\dlF261\u6\d. .sp 2P .LP \fB4\fR \fBInterfaces\fR .sp 1P .RT .PP The interface characteristics (impedances, levels, codes, etc.) should be in accordance with Recommendations\ G.703\ [1], I.430\ [7]\ (optional) and\ V.11\ [3]\ (optional). .PP In addition to providing for terminated measurements the measuring set shall also be capable of monitoring at protected test points on digital equipment. Therefore, a high impedance and/or additional gain must be provided to compensate for the loss at monitoring points already provided on some equipments. .RT .sp 1P .LP 4.1 \fIInterfaces corresponding to Recommendation G.703\fR [1] .sp 9p .RT .PP Three interfaces shall be provided: .RT .LP a) a codirectional interface in accordance with Recommendation\ G.703, \(sc\ 1.2.1\ [1], .LP b) a centralized clock interface in accordance with Recommendation\ G.703, \(sc\ 1.2.2\ [1], .LP c) a contradirectional interface in accordance with Recommendation\ G.703, \(sc\ 1.2.3\ [1]. .sp 1P .LP 4.2 \fIMethod of\fR \fIclock synchronization\fR .sp 9p .RT .PP The following modes of synchronization shall be selectable: .RT .LP a) Lock the digital generator clock rate to that at the input of the receive side of the measuring set (for the codirectional interface). .LP b) Allow the generator clock to free run within the overall allowed frequency tolerances. .LP c) Lock the digital generator clock rate to an external clock signal. (Configuration of input for external clock in accordance with Recommendation\ G.703\ [1].) .sp 1P .LP 4.3 \fIInterface corresponding to Recommendation I.430 [7]\fR .sp 9p .RT .PP For further study. This study should include means for obtaining access to the individual 64\ kbit/s channels at the\ S and T\ interface points. .RT .sp 1P .LP 4.4 \fIInterface corresponding to Recommendation V.11 [3]\fR .sp 9p .RT .PP As an option an interface in accordance with Recommendation\ V.11\ [3] shall be provided. .RT .sp 2P .LP \fB5\fR \fBBit\(hyerror\(hyratio measuring range\fR .sp 1P .RT .PP The receiving equipment of the set should be capable of measuring bit\(hyerror ratios in the range 10\uD\dlF261\u2\d to 10\uD\dlF261\u7\d. The measurement time should be sufficiently long to achieve accurate measurements. In addition, it should be possible to measure bit\(hyerror ratios smaller than 10\uD\dlF261\u7\d; this can be achieved by providing the capability to count cumulative errors. .RT .sp 2P .LP \fB6\fR \fBBlock\(hyerror ratio measurements\fR .sp 1P .RT .PP Optionally, the instrument should be capable to perform block\(hyerror measurements in addition to the bit\(hyerror measurements. If provided it should be possible to measure block\(hyerror ratios in the range 10\uD\dlF261\u0\d to 10\uD\dlF261\u5\d when using the pseudorandom test pattern with a block length of 2047\ bits. .bp .RT .sp 2P .LP \fB7\fR \fBMode of operation\fR .sp 1P .RT .PP The mode of operation should be such that the signal to be tested is first converted into a unipolar (binary) signal in the error measuring instrument and subsequently the bit comparison is made also with a reference signal in binary form. .RT .sp 2P .LP \fB8\fR \fBError evaluation\fR .sp 1P .RT .sp 1P .LP 8.1 \fIMeasurement of\fR \fIerrored time intervals\fR .sp 9p .RT .PP The instrument shall be capable of detecting errored seconds and other errored or error\(hyfree time intervals as defined by Recommendation\ G.821\ [4]. The number of errored or error\(hyfree time intervals in a selectable observation period from 1\ minute to 24\ hours, or continuous, shall be counted and displayed. .PP For this measurement the error detection circuits of the instrument shall be controlled by an internal timer which sets intervals of equal length and which operates independently of the occurrence of errors. .RT .sp 2P .LP 8.2 \fIMeasurement of short\(hyterm mean error ratio\fR .sp 1P .RT .PP 8.2.1 It shall be possible to record the time intervals as defined in Recommendation\ G.821\ [4], during which the bit\(hyerror ratio is less than 1 | (mu | 0\uD\dlF261\u6\d. .sp 9p .RT .PP 8.2.2 It shall be possible to record the one\(hysecond intervals during which the bit\(hyerror ratio is less than 1 | (mu | 0\uD\dlF261\u3\d. .sp 2P .LP \fB9\fR \fBRecording of measurement results\fR .sp 1P .RT .PP As an option an interface shall be provided which allows connecting external equipment for further processing the measuring results. .PP The interface shall comply with Recommendation\ V.24\ [5] or the interface bus according to IEC Publication\ 625\ [6]. .RT .sp 2P .LP \fB10\fR \fBOperating environment\fR .sp 1P .RT .PP The electrical performance requirements shall be met when operating at the climatic conditions as specified in Recommendation\ O.3, \(sc\ 2.1. .RT .sp 2P .LP \fBReferences\fR .sp 1P .RT .LP [1] CCITT Recommendation \fIPhysical/electrical characteristics of\fR \fIhierarchical digital interfaces\fR , Vol.\ III, Rec.\ G.703. .LP [2] CCITT Recommendation \fIModems for synchronous data transmission using\fR \fI60\(hy108 kHz group band circuits\fR , Vol.\ VIII, Rec.\ V.36. .LP [3] CCITT Recommendation \fIElectrical characteristics for balanced\fR \fIdouble\(hycurrent interchange circuits for general use with integrated\fR \fIcircuit equipment in the field of data communications\fR , Vol.\ VIII, Rec.\ V.11. .LP [4] CCITT Recommendation \fIError performance on an international\fR \fIdigital connection forming part of an integrated services digital\fR \fInetwork\fR , Vol.\ III, Rec.\ G.821. .LP [5] CCITT Recommendation \fIList of definitions for interchange\fR \fIcircuits between data terminal equipment and data circuit\(hyterminating\fR \fIequipment\fR , Vol.\ VIII, Rec.\ V.24. .LP [6] IEC Publication 625 \fIAn Interface system for programmable measuring\fR \fIinstruments (byte serial, bit parallel)\fR . .LP [7] CCITT Recommendation \fIBasic user\(hynetwork interface\(hyLayer/Specification\fR , Vol.\ III, Recommendation\ I.430. .bp .sp 2P .LP \fBRecommendation\ O.153\fR .RT .sp 2P .ce 1000 \fBBASIC\ PARAMETERS\ FOR\ THE\ MEASUREMENT\ OF\fR .EF '% Fascicle\ IV.4\ \(em\ Rec.\ O.153'' .OF '''Fascicle\ IV.4\ \(em\ Rec.\ O.153 %' .ce 0 .sp 1P .ce 1000 \fBERROR\ PERFORMANCE\ AT\ BIT\ RATES\ BELOW\ THE\ PRIMARY\ RATE\fR .ce 0 .sp 1P .ce 1000 \fI(Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .PP The requirements for the characteristics of error measuring instrumentation which are described below must be adhered to in order to ensure compatibility between equipments standardized by the CCITT and produced by different manufacturers. .sp 1P .RT .PP While requirements are given for the instrumentation, the realization of the equipment configuration is not covered and should be given careful consideration by the designer and user. In particular, it is not required that all features listed below shall be provided in one instrument. Administrations may select those functions which correspond best to their applications. .PP When selecting functions, Administrations may also consider other Recommendations dealing with error measuring equipment, e.g.\ Recommendations\ O.151 and\ O.152. .RT .sp 2P .LP \fB1\fR \fBGeneral\fR .sp 1P .RT .PP The instrumentation is designed to measure the error performance on data circuits operating at bit rates between\ 0.050 and 168\ kbit/s. The measurement is based on the direct comparison of specified test patterns which are transmitted through the circuit under test with identical patterns generated at the receive side. Synchronous and asynchronous operation shall be possible. .RT .sp 2P .LP \fB2\fR \fBTest patterns\fR .sp 1P .RT .PP The following test patterns are standardized (see Note): .PP \fINote\fR \ \(em\ The use of certain test patterns may be restricted to synchronous or asynchronous operation only. It shall be possible to transmit the patterns for an unlimited time. .RT .sp 1P .LP 2.1 \fI511\(hybit pseudorandom test pattern\fR .sp 9p .RT .PP This pattern is primarily intended for error measurements at bit rates up to 14 | 00\ bit/s (see \(sc\ 3.1 below). .PP The pattern may be generated in a nine\(hystage shift\(hyregister whose 5th and 9th stage outputs are added in a modulo\(hytwo addition stage, and the result is fed back to the input of the first stage. The pattern begins with the first ONE of 9\ consecutive ONES. .RT .LP Number of shift\(hyregister stages \ 9 .LP Length of the pseudorandom sequence \ 2\u9\d \(em 1 = 511 bits .LP Longest sequence of zeros \ 8 (non\(hyinverted signal) .sp 1P .LP 2.2 \fI2047\(hybit pseudorandom test pattern\fR .sp 9p .RT .PP If provided, this pattern is primarily intended for error measurements at bit rates of 64\ kbit/s (see \(sc\ 3.3 below). .PP The pattern may be generated in an eleven\(hystage shift\(hyregister whose 9th and 11th stage outputs are added in a modulo\(hytwo addition stage, and the result is fed back to the input of the first stage. (See also Rec.\ O.152) .RT .LP Number of shift\(hyregister stages \ 11 .LP Length of the pseudorandom sequence \ 2\u1\d\u1\d \(em 1 = 2047\ bits .LP Longest sequence of zeros \ 10 (non\(hyinverted signal) .bp .sp 1P .LP 2.3 \fI1048.575 kbits pseudorandom test pattern\fR .sp 9p .RT .PP This pattern is primarily intended for error measurements at bit rates up to 72\ kbit/s (see \(sc\ 3.2 below). .PP The pattern may be generated in a twenty\(hystage shift\(hyregister whose 3rd and 20th stage outputs are added in a modulo\(hytwo addition stage, and the result is fed back to the input of the first stage. .RT .LP Number of shift\(hyregister stages \ 20 .LP Length of the pseudorandom sequence \ 2\u2\d\u0\d \(em 1 = 1048.575\ kbits .LP Longest sequence of zeros \ 19 (non\(hyinverted signal) .PP \fINote\fR \ \(em\ This test pattern is not identical with the pattern of the same length specified in Recommendation\ O.151. .sp 1P .LP 2.4 \fIFixed test patterns\fR | for continuity tests) \v'3p' .sp 9p .RT .LP \(em Permanent space .LP \(em Permanent mark .LP \(em Alternating space/mark with a ratio of: 1 | | , 1 | | , 1 | | , 3 | | , 7 | | .LP \(em \*QQuick brown fox\*U \(em text (QBF) [1] (asynchronous mode only). .sp 1P .LP 2.5 \fIProgrammable test patterns\fR .sp 9p .RT .PP A freely programmable pattern with a length of at least 1024\ bits is recommended. .RT .sp 2P .LP \fB3\fR \fBBit rates\fR .sp 1P .RT .PP The instrumentation shall provide for measurements at bit rate ranges as specified in the categories below. .RT .sp 1P .LP 3.1 \fIData transmission via telephone\(hytype circuits using modems\fR \v'3p' .sp 9p .RT .LP \(em Bit rate range 50 bit/s to 19 | 00 bit/s. .PP (See Recommendations\ V.5\ [2] and\ V.6\ [3] for details). .PP \fINote\fR \ \(em\ Modems operating at bit rates above 14 | 00 bit/s are not covered by CCITT Recommendations. .RT .sp 1P .LP 3.2 \fIData transmission via group\(hyband circuits using wideband\fR \fImodems\fR \v'3p' .sp 9p .RT .LP \(em Bit rate range 48 kbit/s to 168 kbit/s. .PP (See Recommendations\ V.36\ [4] and\ V.37\ [5] for details). .sp 1P .LP 3.3 \fIData transmisison at and above 64 kbit/s\fR .sp 9p .RT .PP With regard to error performance measurements at 64 kbit/s, relevant information can be found in Recommendation\ O.152. .PP Information on measurements at primary bit rates is contained in Recommendation\ O.151. .RT .sp 1P .LP 3.4 \fIDeviation from nominal bit rate\fR .sp 9p .RT .PP For bit rates up to 9600 bit/s the maximum deviation from the nominal bit rate shall be \(=\ 0.01% if timing is not derived from the object under test. .PP For the higher bit rates the maximum deviation shall be \(=\ 0.002% if timing is not derived from the object under test. .RT .sp 1P .LP 3.5 \fIClock sources\fR .sp 9p .RT .PP Clock signals are provided through the interface, via an external synchronisation input or from an internal clock generator. .bp .RT .sp 2P .LP \fB4\fR \fBInterfaces\fR .sp 1P .RT .PP \fB Depending on the application and the bit rate, one or several of the following interfaces shall be provided: .RT .LP \(em Interface according to Recommendation V.10 (X.26) [6] .LP \(em Interface according to Recommendation V.11 (X.27) [7] .LP \(em Interface according to Recommendations V.24/V.28 [8]\ [9] .LP \(em Interface according to Recommendation V.35\ [10] .LP \(em Interface according to Recommendation V.36 [4] .LP \(em Interface according to Recommendations\ X.21/X.24\ [11]\ [12]. .sp 2P .LP \fB5\fR \fBModes of operation\fR .sp 1P .RT .PP The instrumentation must fully simulate the characteristics of a DTE and/or a DCE in half duplex and/or full duplex mode. This includes the relevant software or hardware handshaking procedures. In synchronous half duplex mode, the test pattern shall be preceded by two or more leading pads (i.e.\ characters with alternating mark and space bits) to enable clock recovery. These pads shall be followed by two or more block\(hysynchronization characters. .PP If the mode of operation requires, it shall be possible to select the parity check conditions even, odd, mark and space. .PP \fINote\fR \ \(em\ The insertion of parity check bits is normally not possible when using pseudorandom test patterns. .RT .sp 2P .LP \fB6\fR \fBBit of synchronization\fR .sp 1P .RT .PP Two modes of synchronization shall be possible: .RT .LP \(em Synchronization by means of a timing signal derived from the object under test (e.g.\ from a modem operating in the synchronous mode). .LP \(em Synchronization from the transitions of the received test signal (e.g.\ when a modem is operating in the nonsynchronous mode). .sp 2P .LP \fB7\fR \fBCodes\fR .sp 1P .RT .PP For encoding the QBF\(hytext or a freely programmable pattern, the following data signal code shall be provided: .RT .LP \(em CCITT Alphabet No. 5 with 7 bits/character [13] .PP For asynchronous operation 1 or 2 stop bits shall be selectable. .sp 2P .LP \fB8\fR \fBError measurements and error evaluation\fR .sp 1P .RT .sp 1P .LP 8.1 \fIBit error measurements\fR .sp 9p .RT .PP The range for error ratio measurements shall be 10\uD\dlF261\u2\d to 10\uD\dlF261\u7\d. The measurement time shall be sufficiently long to achieve accurate results. .PP Error ratios smaller than 10\uD\dlF261\u7\d can be observed by providing the capability to count cumulative errors. .RT .sp 1P .LP 8.2 \fIBlock error measurements\fR .sp 9p .RT .PP It shall be possible to perform block error measurements. The block length shall be selectable to\ 1000 or 10 | 00\ bits or shall be equal to the length of the pseudorandom sequence used for the error test. In addition, a block length of 32 | 68\ bits shall be provided for measurements at bit rates above 14.4\ kbit/s. .PP The range for block error ratio measurements shall be 10\uD\dlF261\u0\d to 10\uD\dlF261\u5\d with measurement times being sufficiently long to achieve accurate results. .RT .sp 1P .LP 8.3 \fISimultaneous measurements\fR .sp 9p .RT .PP It shall be possible to perform bit error ratio and block error ratio measurements simultaneously. .bp .RT .sp 1P .LP 8.4 \fIError performance evaluation\fR .sp 9p .RT .PP The instrumentation shall be capable of detecting errored seconds. The number of errored and error\(hyfree time intervals in a selectable time period from 1\ minute to 24\ hours, or continuous, shall be counted and displayed. .PP For this measurement the error detection circuits of the instrumentation shall be controlled by an internal timer which sets intervals of equal length and which operates independently of the occurrence of errors. .PP The measurement of other error performance parameters and the application of Recommendation\ G.821\ [14] are under study. .RT .sp 2P .LP \fB9\fR \fBMeasurement of distortion\fR .sp 1P .RT .PP If the instrumentation provides for distortion measurements, the following specifications are applicable: .RT .sp 1P .LP 9.1 \fIMeasurement of individual distortion\fR .sp 9p .RT .PP The degrees of early and late individual distortion shall be measured when the instrumentation is operating in the mode in which synchronization is derived from transitions in the received test signal. .PP When using pseudorandom test signals, the measuring error shall be less than \(+- | %. .RT .sp 1P .LP 9.2 \fIMeasurement of bias distortion\fR .sp 9p .RT .PP The instrumentation shall measure bias distortion on reversals (alternating space/mark with a ration of\ 1 | | ). .PP In this mode, the measuring error shall be less than \(+- | %. .RT .sp 2P .LP \fB10\fR \fBRemote control, recording of measurement results\fR .sp 1P .RT .PP As an option, an interface shall be provided which allows remote control of the instrumentation and further processing of the measuring results. .PP If provided, the interface shall comply with the interface bus according to IEC Publication\ 625\ [15] or with Recommendation\ V.24\ [8]. .RT .sp 2P .LP \fB11\fR \fBOperating environment\fR .sp 1P .RT .PP The electrical performance requirements shall be met when operating at climatic conditions as specified in Rec.\ O.3, \(sc\ 2.1. .RT .sp 2P .LP \fBReferences\fR .sp 1P .RT .LP [1] CCITT Recommendation \fIStandardization of international texts for the\fR \fImeasurement of the margin of start\(hystop equipment\fR , Vol.\ VII, Rec.\ R.52. .LP [2] CCITT Recommendation \fIStandardization of data signalling rates for\fR \fIsynchronous data transmission in the general switched telephone network\fR , Vol.\ VIII, Rec.\ V.5. .LP [3] CCITT Recommendation \fIStandardization of data signalling rates for\fR \fIsynchronous data transmission on leased telephone\(hytype circuits\fR , Vol.\ VIII, Rec.\ V.6. .LP [4] CCITT Recommendation \fIModems for synchronous data transmission using\fR \fI60\(hy108 kHz group band circuits\fR , Vol.\ VIII, Rec.\ V.36. .LP [5] CCITT Recommendation \fISynchronous data transmission at a data\fR \fIsignalling rate higher than 72 kbit/s using 60\(hy108 kHz group band circuits\fR ,\fR Vol.\ VIII, Rec.\ V.37. .LP [6] CCITT Recommendation \fIElectrical characteristics for unbalanced\fR \fIdouble\(hycurrent interchange circuits for general use with integrated circuit\fR \fIequipment in the field of data communications\fR , Vol.\ VIII, Rec.\ V.10. .LP [7] CCITT Recommendation \fIElectrical characteristics for balanced\fR \fIdouble\(hycurrent interchange circuits for general use with integrated circuit\fR \fIequipment in the field of data communications\fR , Vol.\ VIII, Rec.\ V.11. .bp .LP [8] CCITT Recommendation \fIList of definitions for interchange circuits\fR \fIbetween data terminal equipment and data circuit\(hyterminating equipment\fR , Vol.\ VIII, Rec.\ V.24. .LP [9] CCITT Recommendation \fIElectrical characteristics for unbalanced\fR \fIdouble\(hycurrent interchange circuits\fR , Vol.\ VIII, Rec.\ V.28. .LP [10] CCITT Recommendation \fIData transmission at 48 kbit/s using 60\(hy108 kHz\fR \fIgroup band circuits\fR , Vol.\ VIII, Rec.\ V.35. .LP [11] CCITT Recommendation \fIInterface between data terminal equipment (DTE)\fR \fIand data circuit\(hyterminating equipment (DCE) for synchronous operation on\fR \fIpublic data networks\fR , Vol.\ VIII, Rec.\ X.21. .LP [12] CCITT Recommendation \fIList of definitions for interchange circuits\fR \fIbetween data terminal equipment (DTE) and data circuit\(hyterminating equipment\fR \fI(DCE) on public data networks\fR , Vol.\ VIII, Rec.\ X.24. .LP [13] CCITT Recommendation \fIInternational Alphabet No. 5\fR , Vol.\ VII, Rec.\ T.50. .LP [14] CCITT Recommendation \fIError performance of an international digital\fR \fIconnection forming part of an integrated digital network\fR , Vol.\ III, Rec.\ G.821. .LP [15] IEC Publication 624 \fIAn interface system for programmable measuring\fR \fIinstruments (byte serial, bit parallel)\fR . \v'6p' .sp 2P .LP \fBRecommendation\ O.161\fR .RT .sp 2P .sp 1P .ce 1000 \fBIN\(hySERVICE\ CODE\ VIOLATION\ MONITORS\ FOR\ DIGITAL\ SYSTEMS\fR .EF '% Fascicle\ IV.4\ \(em\ Rec.\ O.161'' .OF '''Fascicle\ IV.4\ \(em\ Rec.\ O.161 %' .ce 0 .sp 1P .ce 1000 \fI(Geneva, 1980; amended Malaga\(hyTorremolinos, 1984)\fR .sp 9p .RT .ce 0 .sp 1P .LP \fB1\fR \fBGeneral\fR .sp 1P .RT .PP This specification describes an in\(hyservice code violation monitor for the first and second level in the digital transmission hierarchy. .PP The pseudoternary codes to be monitored are alternate mark inversion (AMI), high density bipolar with a maximum of 3 consecutive zeros (HDB3), B6ZS and B8ZS. .RT .sp 2P .LP \fB2\fR \fBDefinition of\fR \fBcode violation\fR .FS According to the definitions of code violations in this Recommendation it should be taken into account that the code violation monitor will not detect zero sequences which violate the relevant coding rules. .FE .sp 1P .RT .sp 1P .LP 2.1 \fIAMI\fR .sp 9p .RT .PP Two consecutive marks of the same polarity. This may not be the absolute number of errors. .RT .sp 1P .LP 2.2 \fIHDB3\fR .sp 9p .RT .PP Two consecutive bipolar violations of the same polarity. This may not be the absolute number of errors. .RT .sp 1P .LP 2.3 \fIB6ZS\fR .sp 9p .RT .PP Two consecutive marks of the same polarity excluding violations caused by the zero substitution code. This may not be the absolute number of errors. .RT .sp 1P .LP 2.4 \fIB8ZS\fR .sp 9p .RT .PP Two consecutive marks of the same polarity excluding violations caused by the zero substitution code . This may not be the absolute number or errors. .bp .RT .sp 2P .LP \fB3\fR \fBInput signal\fR .sp 1P .RT .sp 1P .LP 3.1 \fIInterface\fR .sp 9p .RT .PP The code violation monitor shall be capable of operating at the following bit rates and corresponding interface characteristics as described in the appropriate paragraphs of Recommendation\ G.703\ [1]: .RT .LP a) 1544 kbit/s; .LP b) 6312 kbit/s; .LP c) 2048 kbit/s; .LP d) 8448 kbit/s. .sp 2P .LP 3.2 \fIInstrument operation\fR .sp 1P .RT .PP 3.2.1 The instrument may be equipped to monitor only one or two of the listed codes and operate at the appropriate bit rates for those codes. .sp 9p .RT .sp 2P .LP 3.3 \fIInput sensitivity\fR .sp 1P .RT .PP 3.3.1 The instrument is required to operate satisfactorily under the following input conditions. .sp 9p .RT .PP 3.3.1.1 Input impedances and levels in accordance with Recommendation\ G.703\ [1]. .PP 3.3.1.2 The instrument shall also be capable of monitoring at protected test points on digital equipment. Therefore, a high impedance input and/or additional gain of 30\ dB (40\ dB \(em see Note) shall be provided to compensate for the loss at the monitoring points already provided on some equipment. .PP \fINote\fR \ \(em\ As an option for instruments operating at an interface of 1544\ kbit/s corresponding to the Recommendation cited in\ [1], the additional gain, where provided, shall be 40\ dB. .PP 3.3.1.3 Additionally, the instrument is required to operate satisfactorily, in both the terminated and monitor mode, when connected to an interface output in accordance with Recommendation\ G.703\ [1] via a length of cable which can have an insertion loss of 0\ dB to 6\ dB at the half bit rate of the signal. The insertion loss of the cable at other frequencies will be proportional to\ @ sqrt { fIf\fR~ | } @ . .sp 2P .LP 3.4 \fIInput impedance\fR .sp 1P .RT .PP 3.4.1 The instrument shall have a return loss better than 20\ dB under the conditions listed in Table\ 1/O.161. .sp 9p .RT .ce \fBH.T. [T1.161]\fR .ce TABLE\ 1/O.161 .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(54p) | cw(132p) . { Instrument operating at (kbit/s) } Test conditions _ .T& cw(54p) | lw(72p) | lw(60p) . 1544\fR 100 ohms, nonreactive 20 kHz to 1.6 MHz _ .T& cw(54p) | lw(72p) | lw(60p) . 2048 75/120/130 ohms, nonreactive 40 kHz to 2.5 MHz _ .T& cw(54p) | lw(72p) | lw(60p) . 6312\fR 75/110 ohms, nonreactive 100 kHz to 6.5 MHz _ .T& cw(54p) | lw(72p) | lw(60p) . 8448 75 ohms, nonreactive 100 kHz to 10.0 MHz _ .TE .nr PS 9 .RT .ad r \fBTable 1/O.161 [T1.161], p. \fR .sp 1P .RT .ad b .RT .LP .bp .sp 2P .LP 3.5 \fISignal input gating\fR .sp 1P .RT .PP 3.5.1 The instrument shall incorporate a sampling circuit, operated from the incoming digital signal, such that the instrument senses only the voltages which are present during a short gating period at the midpoint of each digit time slot. .sp 9p .RT .sp 2P .LP 3.6 \fIInput\fR \fIjitter\fR \fItolerance\fR .sp 1P .RT .PP 3.6.1 The instrument shall be able to tolerate the lower limit of maximum tolerable input jitter specified in the appropriate paragraph of Recommendation\ G.703\ [1]. .sp 9p .RT .sp 2P .LP \fB4\fR \fBDisplay\fR .sp 1P .RT .PP 4.1 The instrument shall incorporate an indicator to show the presence of a digital signal of correct amplitude and bit rate. .sp 9p .RT .PP 4.2 The code violation rate shall be indicated in the range\ 1 in 10\u3\d to at least 1 in 10\u6\d. Indication of code violations, occurring in the input signal and detected as defined in \(sc\ 2 above, shall be determined by counting the number of code violations that occur during the period of at least 10\u6\d digit time slots. .PP 4.3 It shall be possible to indicate the sum of the code violations. This facility will not be required at the same time as the code violation rate is being counted and displayed. .PP 4.4 The count capacity shall be 99 999 and a separate indicator shall be given if the count exceeds this figure. .PP 4.5 The counting sequence shall be started by operating a \*Qstart\*U control and shall be stopped by a \*Qstop\*U control. .PP 4.6 The counter, and its display, shall be capable of being reset. .sp 2P .LP \fB5\fR \fBInstrument check\fR .sp 1P .RT .PP 5.1 A check facility shall be provided. This facility is to enable a check to be made of the display, counter and recorder output and optionally of the instrument input circuits. .sp 9p .RT .PP 5.2 Where the optional check of the input circuits is provided, the method of introducing code violations into the input digital signal shall be agreed. The violations shall be as defined in \(sc\ 2 above. .sp 2P .LP \fB6\fR \fBRecorder output\fR .sp 1P .RT .PP 6.1 An output signal may optionally be provided by the instrument to enable the status of the digital signal to be recorded externally in analogue and/or digital form. .sp 9p .RT .PP 6.2 For the analogue output, the signal shall vary corresponding to the measured result. .PP 6.3 If the instrument has an analogue output, appropriate means for calibrating the external recorder shall be provided. .PP 6.4 A possible arrangement relating the status of the digital input signal to the d.c. output signal is given in Table\ 2/O.161. The actual arrangement will depend upon the count period specified for the instrument (see \(sc\ 4.2 above). .PP 6.5 For the digital output of the measurement result, where provided, a parallel signal in binary coded decimal (BCD) form with transistor\(hytransistor logic (TTL) levels shall be used. .sp 2P .LP \fB7\fR \fBOperating environment\fR .sp 1P .RT .PP The electrical performance requirements shall be met when operating at the climatic conditions as specified in Recommendation\ O.3, \(sc\ 2.1. .bp .RT .ce \fBH.T. [T2.161]\fR .ce TABLE\ 2/O.161 .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(90p) | cw(30p) | cw(30p) . Status Deflection (mA or volts) Tolerance (mA or volts) _ .T& lw(90p) | cw(30p) | cw(30p) . No signal 0\fB.5\fR \(em _ .T& lw(90p) | cw(30p) | cw(30p) . Valid signal 5\fB.5\fR \(+- | .2 _ .T& lw(90p) | cw(30p) | cw(30p) . { Violation rate \(>=" 1 | (mu | 0\uD\dlF261\u3\d } 2\fB.5\fR \(+- | .2 _ .T& lw(90p) | cw(30p) | cw(30p) . { Violation rate \(>=" 1 | (mu | 0\uD\dlF261\u4\d } 2.5 \(+- | .2 _ .T& lw(90p) | cw(30p) | cw(30p) . { Violation rate \(>=" 1 | (mu | 0\uD\dlF261\u5\d } 3\fB.5\fR \(+- | .2 _ .T& lw(90p) | cw(30p) | cw(30p) . { Violation rate \(>=" 1 | (mu | 0\uD\dlF261\u6\d } 3.5 \(+- | .2 _ .T& lw(90p) | cw(30p) | cw(30p) . Single code violations 4\fB.5\fR \(+- | .2 _ .TE .nr PS 9 .RT .ad r \fBTABLEAU\ 2/O.161 [T2.161], p. 7\fR .sp 1P .RT .ad b .RT .sp 2P .LP \fBReference\fR .sp 1P .RT .LP [1] CCITT Recommendation \fIPhysical/electrical characteristics of\fR \fIhierarchical digital interfaces\fR , Vol.\ III, Rec.\ G.703. \v'1P' .sp 2P .LP \fBRecommendation\ O.162\fR .RT .sp 2P .sp 1P .ce 1000 \fBEQUIPMENT TO PERFORM IN SERVICE MONITORING\fR \fBON 2048 kbit/s SIGNALS\fR .EF '% Fascicle\ IV.4\ \(em\ Rec.\ O.162'' .OF '''Fascicle\ IV.4\ \(em\ Rec.\ O.162 %' .ce 0 .sp 1P .ce 1000 \fI(Geneva, 1980, amended Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .LP \fB1\fR \fBGeneral\fR .sp 1P .RT .PP 1.1 This specification describes an instrument for performing in\(hyservice error tests on 2\ Mbit/s signals having frame structures that are in accordance with Recommendation\ G.704 [1]. .sp 9p .RT .PP 1.2 The instrument is required to monitor a 2048\(hykbit/s HDB3 encoded signal, display any inherent alarm condition in the signal and be capable of counting errors in the frame alignment signal. .PP 1.3 The instrument may also, if so desired, count and display HDB3 code violations as a separate facility. .PP 1.4 The instrument is required to monitor any cyclic redundancy check\ (CRC) procedure signals, in accordance with Recommendation\ G.704\ [1], conveyed within the frame alignment signal, and time slot\ 0 (TSO) of frames not containing the frame alignment signal. .PP 1.5 As an option the instrument may provide access to the information bits conveyed in any selected time slot. .bp .sp 1P .LP 1.6 \fIHDB3 decoding strategy\fR .sp 9p .RT .PP When necessary, the received digital signal shall be decoded by the instrument in a manner such that, when sampling the signal, on recognition of\ 2 consecutive zeros (spaces) followed by a bipolar violation, the decoder shall substitute\ 4 consecutive zeros in place of the bipolar violation and the\ 3 preceding digits. .RT .sp 2P .LP \fB2\fR \fBInput signal\fR .sp 1P .RT .sp 1P .LP 2.1 \fIInterface\fR .sp 9p .RT .PP The instrument shall be capable of operating with the interface at 2048\ kbit/s corresponding to Recommendation\ G.703\ [2], \(sc\ 6. .RT .sp 2P .LP 2.2 \fIInput sensitivity\fR .sp 1P .RT .PP 2.2.1 The instrument is required to operate satisfactorily under the following input conditions. .sp 9p .RT .PP 2.2.1.1 Input impedances and levels in accordance with Recommendation\ G.703\ [2]. .PP 2.2.1.2 The instrument shall also be capable of monitoring at protected test points on digital equipment. Therefore, a high impedance input and/or additional gain of 30\ dB shall be provided to compensate for the loss at the monitoring points already provided on some equipment. .PP 2.2.1.3 Additionally the instrument is required to operate satisfactorily, in both the terminated and monitor mode, when connected to an interface output in accordance with Recommendation\ G.703\ [2] via a length of cable which can have an insertion loss of 0\ dB to 6\ dB at the half bit rate of the signal. The insertion loss of the cable at other frequencies will be proportional to\ @ sqrt { fIf\fR~ | } @ . .sp 2P .LP 2.3 \fIInput impedance\fR .sp 1P .RT .PP 2.3.1 The instrument shall have a return loss of better than 20\ dB against a nonreactive 75/120/130\(hyohm resistor over a frequency range of 40\ kHz to 2500\ kHz. .sp 9p .RT .sp 2P .LP 2.4 \fISignal input gating\fR .sp 1P .RT .PP 2.4.1 The instrument shall incorporate a timing recovery circuit, operated from the incoming digital signal, such that the instrument senses only the voltages which are present during a short gating period at the midpoint of each digit time slot. .sp 9p .RT .sp 2P .LP 2.5 \fIInput\fR \fIjitter\fR \fItolerance\fR .sp 1P .RT .PP 2.5.1 The instrument shall be able to tolerate the lower limit of maximum tolerable input jitter specified in Recommendation\ G.823\ [3]. .sp 9p .RT .sp 2P .LP \fB3\fR \fBFacilities\fR .sp 1P .RT .PP 3.1 The instrument shall incorporate fault indications to meet the alarm strategies of equipments meeting Recommendation\ G.732\ [4]. .sp 9p .RT .PP 3.2 A possible fault indication plan is illustrated in \(sc\ 3.3 below. All fault indicators are normally extinguished. .sp 2P .LP 3.3 \fIFault indication plan\fR .sp 1P .RT .sp 1P .LP 3.3.1 \fIInput signal failure\fR .sp 9p .RT .PP A fault indication shall be given if more than 10\ consecutive zeros are detected. .bp .RT .sp 1P .LP 3.3.2 \fIAlarm indication signal (AIS)\fR .sp 9p .RT .PP The instrument shall recognize a signal containing less than 3 zeros in a 2\(hyframe period (512\ bits) as a valid AIS signal and the appropriate indicator shall be lit. .PP The strategy for the detection of the presence of an AIS shall be such that the AIS is detectable even in the presence of a code violation rate of 1 in 10\u3\d. However, a signal with all bits in the 1s state, except the frame alignment signal (FAS), shall not be mistaken for a valid AIS. .RT .sp 2P .LP 3.3.3 \fIFrame\fR .sp 1P .RT .PP 3.3.3.1 In the event of a loss of frame alignment, as defined in Recommendation\ G.706\ [5], \(sc\ 4, the instrument shall recognize the loss and the appropriate indicator shall be lit. .sp 9p .RT .PP 3.3.3.2 In the event of recovery of frame alignment, as defined in Recommendation\ G.706\ [5], \(sc\ 4, the indicator shall be extinguished. .PP \fINote\fR \ \(em\ The instrument shall be able to synchronize to frames with or without CRC bits. .sp 2P .LP 3.3.4 \fIErrors in the\fR \fIframe alignment signal\fR .sp 1P .RT .PP 3.3.4.1 The instrument shall have a means of indicating bit error rates, e.g.\ 1\ \(mu\ 10\uD\dlF261\u3\d, 1\ \(mu\ 10\uD\dlF261\u4\d, 1\ \(mu\ 10\uD\dlF261\u5\d and illuminate the appropriate indicator. .sp 9p .RT .PP The indication of bit error rates occurring in the received decoded signal and detected as incorrect frame alignment signals shall comply with the limits given in Table\ 1/O.162. The requirements in the table shall apply on the assumption that the average bit error rates are present for the whole of the counter measurement period. .ce \fBH.T. [T1.162]\fR .ce TABLE\ 1/O.162 .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(42p) | cw(42p) | cw(54p) sw(54p) , ^ | ^ | c | c. Bit error rate indication { Average bit error rates in decoded signal } { Probability of indication illuminating or extinguishing within the periods stated below } Illuminate Extinguish _ .T& cw(42p) | cw(42p) | cw(54p) | cw(54p) . 1 | (mu | 0\uD\dlF261\u3\d { 1 | (mu | 0\uD\dlF261\u3\d 5 | (mu | 0\uD\dlF261\u4\d 1 | (mu | 0\uD\dlF261\u4\d } { 50% within 0.3 s \ 5% within 0.3 s \(em } { \ 5% within 0.3 s \(em 95% within 0.3 s } _ .T& cw(42p) | cw(42p) | cw(54p) | cw(54p) . 1 | (mu | 0\uD\dlF261\u4\d { 1 | (mu | 0\uD\dlF261\u4\d 5 | (mu | 0\uD\dlF261\u5\d 1 | (mu | 0\uD\dlF261\u5\d } { 50% within 3 s \ 5% within 3 s \(em } { \ 5% within 3 s \(em 95% within 3 s } _ .T& cw(42p) | cw(42p) | cw(54p) | cw(54p) . 1 | (mu | 0\uD\dlF261\u5\d { 1 | (mu | 0\uD\dlF261\u5\d 5 | (mu | 0\uD\dlF261\u6\d 1 | (mu | 0\uD\dlF261\u6\d } { 50% within 30 s \ 5% within 30 s \(em } { \ 5% within 30 s \(em 95% within 30 s } _ .TE .nr PS 9 .RT .ad r \fBTable 1/O.162 [T1.162] p. \fR .sp 1P .RT .ad b .RT .PP 3.3.4.2 It shall also be possible to count the sum of the errors indicated. The count capacity shall be 99 | 99. A\ separate indication shall be given if the count exceeds this figure. .sp 2P .LP 3.3.5 \fIMultiframe\fR .sp 1P .RT .PP 3.3.5.1 In the event of a loss of multiframe alignment, as defined in Recommendation\ G.732\ [4], \(sc\ 5.2, the instrument shall recognize the loss and the appropriate indicator shall be lit. .sp 9p .RT .PP 3.3.5.2 In the event of recovery of multiframe alignment, as defined in Recommendation\ G.732\ [4], \(sc\ 5.2, the indicators shall be extinguished. .bp .PP 3.3.5.3 If time slot 16 is used for common channel signalling, the multiframe alignment signal is not present in a nominal input signal to the instrument. In this case it shall be possible to inhibit the loss of multiframe indicator in order to prevent false alarm indications. .sp 1P .LP 3.3.6 \fIDistant alarm\fR .sp 9p .RT .PP The instrument shall recognize the distant alarm condition as defined in Recommendation\ G.732\ [4] (bit\ 3 of time slot\ 0 in frames alternate to those containing the frame alignment signal for at least 2\ consecutive occasions and recognized within 4\ consecutive occasions) and the appropriate indicator shall be lit. .RT .sp 2P .LP 3.3.7 \fIDistant multiframe alarm\fR .sp 1P .RT .PP 3.3.7.1 The instrument shall recognize the distant multiframe alarm condition as defined in Recommendation\ G.732\ [4] (bit\ 6 of time slot\ 16, frame\ 0 for at least 2\ consecutive occasions and recognized within 3\ consecutive occasions) and the appropriate indicator shall be lit. .sp 9p .RT .PP 3.3.7.2 If time slot 16 is used for common channel signalling, bit\ 6 will be continuously in state\ 1. In this case it shall be possible to inhibit the distant multiframe alarm in order to prevent false alarm indications. .sp 2P .LP 3.4 \fICyclic redundancy check procedure\fR .sp 1P .RT .PP 3.4.1 Where a cyclic redundancy check (CRC) procedure in accordance with Recommendation\ G.704 [1] is implemented within the\ 2\ Mbit/s signal the instrument shall provide the features detailed in \(sc\(sc\ 3.4.2, 3.4.3 and\ 3.4.4. .sp 9p .RT .PP 3.4.2 The instrument shall indicate the presence of CRC framing bits. .PP 3.4.3 The instrument shall have a means of indicating bit error rates of 1\ \(mu\ 10\uD\dlF261\u5\d, 1\ \(mu\ 10\uD\dlF261\u6\d and 1\ \(mu\ 10\uD\dlF261\u7\d and shall cause the appropriate indicator to be illustrated under the conditions defined. .PP The indication of bit error rates occurring in the received decoded signal and detected by means of the CRC procedure information shall comply with the limits given in Table\ 2/O.162. .ce \fBH.T. [T2.162]\fR .ce TABLE\ 2/O.162 .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(42p) | cw(42p) | cw(54p) sw(54p) , ^ | ^ | c | c. Bit error rate indication { Average bit error rate in decoded signal } { Probability of indication illuminating or extinguishing within the periods stated below } Illuminate Extinguish _ .T& cw(42p) | cw(42p) | cw(54p) | cw(54p) . 1 | (mu | 0\uD\dlF261\u5\d { 1 | (mu | 0\uD\dlF261\u5\d 5 | (mu | 0\uD\dlF261\u6\d 1 | (mu | 0\uD\dlF261\u6\d } { 50% within 1 s \ 5% within 1 s \(em } { \ 5% within 1 s \(em 95% within 1 s } _ .T& cw(42p) | cw(42p) | cw(54p) | cw(54p) . 1 | (mu | 0\uD\dlF261\u6\d { 1 | (mu | 0\uD\dlF261\u6\d 5 | (mu | 0\uD\dlF261\u7\d 1 | (mu | 0\uD\dlF261\u7\d } { 50% within 10 s \ 5% within 10 s \(em } { \ 5% within 10 s \(em 95% within 10 s } _ .T& cw(42p) | cw(42p) | cw(54p) | cw(54p) . 1 | (mu | 0\uD\dlF261\u7\d { 1 | (mu | 0\uD\dlF261\u7\d 5 | (mu | 0\uD\dlF261\u8\d 1 | (mu | 0\uD\dlF261\u8\d } { 50% within 100 s \ 5% within 100 s \(em } { \ 5% within 100 s \(em 95% within 100 s } _ .TE .nr PS 9 .RT .ad r \fBTable 2/O.162 [T2.162], p. \fR .sp 1P .RT .ad b .RT .PP 3.4.4 It shall also be possible to count the sum of errors indicated. The count capacity shall be 99\ 999. A separate indication shall be given if the count exceeds this figure. .bp .sp 2P .LP 3.5 \fICode violation detection\fR .sp 1P .RT .sp 1P .LP 3.5.1 \fIDefinition of an\fR \fIHDB3 code violation\fR .sp 9p .RT .PP Two consecutive bipolar violations of the same polarity. This may not be the absolute number of errors. .RT .PP 3.5.2 When used as an HDB3 code violation detector the instrument shall incorporate an indicator to indicate the presence of a digital signal of correct amplitude and bit rate. .PP 3.5.3 The code violation rate shall be indicated in the range\ 1 in 10\u3\d to at least 1 in 10\u6\d. Indications of code violations occurring in the input signal and detected as defined in \(sc\ 3.5.1 above, shall be determined by counting the number of code violations that occur during the period of at least 10\u6\d time slots. .PP 3.5.4 It shall be possible to indicate the sum of the code violations. This facility will not be required at the same time as the code violation rate is being counted and displayed. .PP 3.5.5 The count capacity shall be 99 | 99 and a separate indication shall be given if the count exceeds this figure. .sp 1P .LP 3.6 \fIPerformance indications\fR .sp 9p .RT .PP As an option the instrument shall be capable of providing performance information in accordance with G.821 [6]. .RT .sp 1P .LP 3.7 \fILamp lock \(em Lamp auto reset\fR .sp 9p .RT .PP A facility shall be provided whereby the fault indication lamps either clear automatically when the fault condition clears or remain lit until a manual reset is operated. .RT .sp 1P .LP 3.8 \fITime slot access\fR .sp 9p .RT .PP As an option it shall be possible to access, at an external interface, the contents of any selected time slot, including time slot\ 16. An external interface meeting the requirements of a co\(hydirectional interface, as defined in Recommendation\ G.703 [2], is preferred. .RT .sp 2P .LP \fB4\fR \fBDisplay\fR .sp 1P .RT .PP 4.1 The counting sequence shall be started by operating a \*Qstart\*U control and shall be stopped by a \*Qstop\*U control. .sp 9p .RT .PP 4.2 References to counters and displays being illuminated and extinguished does not imply that \*Qlight emitting\*U displays are essential. .PP 4.3 The counter, and its display, shall be capable of being reset. .sp 2P .LP \fB5\fR \fBAlarm function check\fR .sp 1P .RT .PP A method of introducing fault conditions into the incoming digital signal, in order to check the correct functioning of the instrument, shall be considered. .RT .sp 2P .LP \fB6\fR \fBAlarm output signal\fR .sp 1P .RT .PP As an option, an interface shall be provided to enable an external device, e.g. printer, to be connected to the instrument to allow recording of the status of the digital signal input to the instrument. .PP An interface in accordance with Recommendation\ V.24\ [7] or V.28\ [8], carrying suitably abbreviated, plain text messages in ASCII/T.50\ [9] coded format according to the requirements of Recommendation\ V.4\ [10] is preferred. .RT .sp 2P .LP \fB7\fR \fBOperating environment\fR .sp 1P .RT .PP The electrical performance requirements shall be met when operating within the climatic conditions specified in Recommendation\ O.3, \(sc\ 2.1. .bp .RT .sp 2P .LP \fBReferences\fR .sp 1P .RT .LP [1] CCITT Recommendation \fISynchronous frame structures used at primary and\fR \fIsecondary hierarchical levels\fR , Vol.\ III, Rec.\ G.704. .LP [2] CCITT Recommendation \fIPhysical/electrical characteristics of\fR \fIhierarchical digital interfaces\fR , Vol.\ III, Rec.\ G.703. .LP [3] CCITT Recommendation \fIThe control of jitter and wander within\fR \fIdigital networks which are based on the 2048\ kbit/s hierarchy\fR Vol.\ III, Rec.\ G.823. .LP [4] CCITT Recommendation \fICharacteristics of primary PCM multiplex\fR \fIequipment operating at 2048\ kbit/s\fR , Vol.\ III, Rec.\ G.732. .LP [5] CCITT Recommendation \fIFrame alignment and CRC procedures relating to\fR \fIframes defined in Rec.\ G.704\fR , Vol.\ III, Rec.\ G.706. .LP [6] CCITT Recommendation \fIError performance of an international digital\fR \fIconnection forming part of an integrated digital network\fR , Vol.\ III, Rec.\ G.821. .LP [7] CCITT Recommendation \fIList of definitions for interchange circuits\fR \fIbetween data terminal equipment and data circuit\(hyterminating equipment\fR , Vol.\ VIII, Rec.\ V.24. .LP [8] CCITT Recommendation \fIElectrical characteristics or unbalanced\fR \fIdouble\(hycurrent interchange circuits\fR , Vol. VIII, Rec.\ V.28. .LP [9] CCITT Recommendation \fIInternational Alphabet No.\ 5\fR , Vol.\ VII, Rec.\ T.50. .LP [10] CCITT Recommendation \fIGeneral structure of signals of International\fR \fIAlphabet No.\ 5 code for character oriented data transmission over public\fR \fItelephone networks\fR , Vol.\ VIII, Rec.\ V.4. \v'6p' .sp 2P .LP \fBRecommendation\ O.163\fR .RT .sp 2P .sp 1P .ce 1000 \fBEQUIPMENT TO PERFORM IN\(hySERVICE MONITORING\fR \fBON 1544 kbit/s SIGNALS\fR .EF '% Fascicle\ IV.4\ \(em\ Rec.\ O.163'' .OF '''Fascicle\ IV.4\ \(em\ Rec.\ O.163 %' .ce 0 .sp 1P .ce 1000 \fI(Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .LP \fB1\fR \fBGeneral\fR .sp 1P .RT .PP 1.1 This specification describes frame alignment signal monitoring equipment for 1544\ kbit/s frame structures that are in accordance with Recommendation\ G.704\ [1]. This equipment is intended to monitor 12\(hyframe multiframe (superframe format\ \(em\ SF) or 24\(hyframe multiframe (extended superframe format\ \(em\ ESF) structures having either AMI or B8ZS line codes as defined in\ \(sc\ 2 of Recommendation\ G.703 [2]. .sp 9p .RT .PP 1.2 This equipment shall provide the following capabilities: .sp 9p .RT .LP a) monitor and display the error performance of the frame alignment signal; .LP b) detect and accumulate the counts of occurrences of loss of frame alignment; .LP c) measure and display the error performance of 24\(hyframe multiframe signals by monitoring the cyclic redundancy check (CRC\(hy6) bits and performing a CRC\(hy6 procedure in accordance with Recommendation\ G.704 [1] and as described below; .LP d) detect and display the various alarm or fault conditions including loss of signal, loss of frame alignment, and other alarm conditions indicated by specific bit patterns. .PP 1.3 The equipment may optionally provide the following additional capabilities: .sp 9p .RT .LP a) detect and display the code violations in the 1544\ kbits signal in accordance with Recommendation\ O.161; .LP b) provide an external interface for extracting the information bits conveyed in any selected channel time slot; .LP c) provide an external interface for extracting the 4\ kbit/s data link bits defined in the 24\(hyframe multiframe structure; .LP d) provide an external interface for extracting the signalling bits in the 12\(hyframe and 24\(hyframe structures. .bp .sp 2P .LP \fB2\fR \fBInput requirements\fR .sp 1P .RT .sp 1P .LP 2.1 \fIInterface\fR .sp 9p .RT .PP The specification of protected monitoring points is under study in SG\ XV and SG\ IV. .FE The monitoring equipment shall be capable of operating with a test load impedance at a 1544\ kbit/s interface as defined in\ \(sc\ 2 of Recommendation\ G.703 [2]. It shall also be capable of operating when connected to protected monitoring points (see also Recommendation\ G.772\ [3]). .RT .sp 2P .LP 2.2 \fIInput impedance\fR .sp 1P .RT .sp 1P .LP 2.2.1 \fIInput impedance\fR | (resistive) \ 100\ ohms .sp 9p .RT .sp 1P .LP 2.2.2 \fIReturn loss (20\ kHz to 1600\ kHz)\fR \ >\ 20\ dB .sp 9p .RT .sp 1P .LP 2.3 \fIInput sensitivity\fR .sp 9p .RT .PP As a minimum, the monitoring equipment shall operate properly in the line terminating mode over the range of bit rates, pulse shapes and signal levels defined in\ \(sc\ 2 of Recommendation\ G.703 [2]. It shall also be equipped with an additional gain to compensate for the isolation loss incurred at protected monitoring points (see also Recommendation\ G.772 [3]). A signal level indicator, or other means, shall be provided for the proper adjustment of input sensitivity. .RT .sp 1P .LP 2.4 \fIInput jitter tolerance\fR .sp 9p .RT .PP The monitoring equipment shall be able to tolerate input jitter specified in Table\ 2/G.824 [4] without degradation of measuring accuracy. .RT .sp 1P .LP 2.5 \fIInput line codes\fR .sp 9p .RT .PP The monitoring equipment is intended for use with both AMI and B8ZS line codes. The instrument shall have the capability to select either AMI or B8ZS, through a switch or other appropriate means. The instrument should indicate when it is receiving B8ZS when switched to the AMI mode, and vice versa. .RT .LP \fB3\fR \fBDetection, measurement, and indication requirements\fR .sp 1P .RT .sp 2P .LP 3.1 \fIDetection and indication of fault conditions\fR .sp 1P .RT .sp 1P .LP 3.1.1 \fILoss of line signal\fR .sp 9p .RT .PP Under study. .RT .sp 1P .LP 3.1.2 \fILoss of frame alignment\fR .sp 9p .RT .PP The equipment shall recognize the loss of frame alignment as defined in Recommendation\ G.706 [5], and an appropriate indication shall be given. .RT .sp 1P .LP 3.1.3 \fIRecovery of frame alignment\fR .sp 9p .RT .PP The procedure for determining recovery of frame alignment shall be in accordance with Recommendation\ G.706 [5]. When frame recovery is complete, the indication of loss of frame alignment shall cease. .RT .sp 1P .LP 3.1.4 \fIAlarm indication signal (AIS) from an upstream failure\fR .sp 9p .RT .PP The equipment shall recognize the presence of an alarm indication signal (AIS) indicating an upstream failure, and an appropriate indication shall be given. The binary equivalent of the AIS corresponds to an all ones signal. The strategy for the detection of the presence of an AIS shall be such that with a high probability, it is detected even in the presence of a code violation ratio of\ 1 in\ 1000. .bp .RT .sp 1P .LP 3.1.5 \fIDistant alarm indication signal (DAIS)\fR .sp 9p .RT .PP The equipment shall recognize the presence of distant alarm indication signal as defined in Recommendation\ G.733 [6], \(sc\ 4.2.4 for both 12\(hyframe and 24\(hyframe multiframe signals, and an appropriate indication shall be given. The strategy for the detection of the presence of this distant alarm indication signal shall be such that with a high probability, it is detected even in the presence of a code violation ratio of\ 1 in 1000. .RT .sp 2P .LP 3.2 \fIFrame alignment signal (FAS) error performance measurements\fR .sp 1P .RT .sp 1P .LP 3.2.1 \fICount of errored seconds\fR .sp 9p .RT .PP The equipment shall be capable of counting the number of one second intervals in which one or more errors occur in the FAS bits associated with the 12\(hyframe or 24\(hyframe structures as defined in Recommendation\ G.704 [1]. The number of errored seconds in a selectable time period (see\ \(sc\ 4.1) shall be counted and displayed. The equipment shall establish one\(hysecond intervals independent of the occurrence of errors. .RT .sp 1P .LP 3.2.2 \fICount of errors\fR .sp 9p .RT .PP The equipment shall be capable of counting the number of FAS bit errors occurring in a selectable time period (see\ \(sc\ 4.1). .RT .sp 2P .LP 3.3 \fICRC\(hy6 error performance monitoring\fR .sp 1P .RT .sp 1P .LP 3.3.1 \fICount of errored seconds\fR .sp 9p .RT .PP The equipment shall be capable of counting the number of one\(hysecond intervals in which one or more CRC\(hy6 violations are detected in 24\(hyframe multiframe signals using the CRC\(hy6 procedure defined in Recommendation\ G.704 [1] and G.706 [5]. The number of errored seconds in a selectable time period shall be counted and displayed. The equipment shall establish one\(hysecond intervals independent of the occurrence of errors. .RT .sp 1P .LP 3.3.2 \fIPerformance indications\fR .sp 9p .RT .PP As an option the instrument shall be capable of providing performance information in accordance with Recommendation\ G.821 [7]. .RT .sp 1P .LP 3.3.3 \fIEstimate of bit\(hyerror\(hyratio\fR .sp 9p .RT .PP This equipment shall optionally be capable of providing an estimate of the bit\(hyerror\(hyratio performance of 24\(hyframe multiframe signals in the range 10\uD\dlF261\u4\d to 10\uD\dlF261\u7\d by detecting CRC\(hy6 violations. In performing this measurement, it shall be assumed that only one bit\(hyerror has occurred each time a CRC\(hy6 violation is detected. It is noted that this may not be an accurate estimate since more than one bit\(hyerror may occur within a 24\(hyframe multiframe, due to the bursty nature of error occurrences. .PP The time interval for each bit\(hyerror\(hyratio measurement that is within the required range of the equipment shall be sufficiently long to include at least ten CRC violations. .RT .sp 1P .LP 3.3.4 \fICount of errors\fR .sp 9p .RT .PP The equipment shall also be capable of counting the number of CRC\(hy6 violations occurring in a selectable time period (see\ \(sc\ 4.1). .RT .sp 1P .LP 3.4 \fILoss of frame\(hyalignment count\fR .sp 9p .RT .PP The equipment shall be capable of counting the occurrences of loss of frame alignment over a selectable time period (see\ \(sc\ 4.1). Error counters shall be disabled during intervals of loss of frame alignment. .bp .RT .sp 1P .LP 3.5 \fIMeasurement of code violations\fR .sp 9p .RT .PP If the measurement of 1544\ kbit/s code violations is included, the equipment shall meet the requirements of Recommendation\ O.161. .RT .sp 1P .LP 3.6 \fIChannel time slot access\fR .sp 9p .RT .PP As an option, receiving access may be provided to a selected 64\ kbit/s channel at an external interface. An interface meeting the requirements of a co\(hydirectional interface output port defined in Recommendation\ G.703\ [2], is preferred. In addition a centralized clock interface as defined in Recommendation\ G.703 [2] may be provided. .RT .sp 1P .LP 3.7 \fI4 kbit/s data link access\fR .sp 9p .RT .PP Under study. .RT .sp 1P .LP 3.8 \fISignaling bit access\fR .sp 9p .RT .PP Under study. .RT .sp 2P .LP \fB4\fR \fBControl and display requirements\fR .sp 1P .RT .sp 1P .LP 4.1 \fIMeasurement timer\fR .sp 9p .RT .PP A measurement interval timer shall be provided for the convenience of the user when counting errors. The timer shall be adjustable from\ 5 minutes to\ 24 hours in steps of one minute or continuous. Manual \*Qstart\*U and \*Qstop\*U controls shall also be provided. .RT .sp 1P .LP 4.2 \fICount registers\fR .sp 9p .RT .PP The count registers shall have a capacity of at least 99999. A separate means for indicating overflow shall be provided. Each of the registers shall be capable of being independently reset. A separate register shall be provided for each parameter or condition listed in\ \(sc\(sc\ 3.1 through\ 3.4. .RT .sp 1P .LP 4.3 \fISelection of multiframe structure\fR .sp 9p .RT .PP A control shall be provided to permit a user to select whether the 12\(hyframe or 24\(hyframe multiframe structure is being monitored. As an option the equipment may automatically sense and display whether the signal being monitored is a 12\(hyframe, 24\(hyframe or neither multiframe structure. .RT .sp 1P .LP 4.4 \fILock/reset of displays\fR .sp 9p .RT .PP For each of the fault condition indications given in\ \(sc\ 3.1 means shall be provided whereby the display will remain visible until a manual reset is operated. .RT .sp 2P .LP \fB5\fR \fBMonitoring equipment self diagnostics\fR .sp 1P .RT .PP 5.1 As an option, an internal self diagnostic system to check for correct functioning of the instrument, shall be provided. .sp 9p .RT .sp 2P .LP \fB6\fR \fBInterface for remote control and measurement results\fR .sp 1P .RT .PP 6.1 As an option, an interface shall be provided for remote control of the frame signal monitoring equipment, and transmission of measurement results. If provided, the interface bus shall comply with one of the following: .sp 9p .RT .LP a) ANSI/IEEE Std 488\(hy1978 [8] .LP b) IEC Publication 625 [9] .LP c) ANSI/EIA\(hy232\(hyD\(hy1986 [10]. .bp .sp 2P .LP \fB7\fR \fBOperating environment\fR .sp 1P .RT .PP The electrical performance requirements shall be met when operating under climatic conditions as specified in Recommendation\ O.3, \(sc\ 2.1. .RT .sp 2P .LP \fBReferences\fR .sp 1P .RT .LP [1] CCITT Recommendation \fISynchronous frame structures used at primary and\fR \fIsecondary hierarchical levels\fR , Vol.\ III, Rec.\ G.704. .LP [2] CCITT Recommendation \fIPhysical/electrical characteristics of\fR \fIhierarchical digital interfaces\fR , Vol.\ III, Rec.\ G.703. .LP [3] CCITT Recommendation \fIDigital protected monitor points\fR , Vol.\ III, Rec.\ G.772. .LP [4] CCITT Recommendation \fIThe control of jitter and wander within digital\fR \fInetworks which are based on the 1544\ kbit/s hierarchy\fR , Vol.\ III, Rec.\ G.824. .LP [5] CCITT Recommendation \fIFrame alignment and cyclic redundancy check\fR \fI(RCR) procedures relating to basic frame structures defined in\fR \fIRecommendation G.704\fR , Vol.\ III, Rec.\ G.706. .LP [6] CCITT Recommendation \fICharacteristics of primary PCM multiplex\fR \fIequipment operating at 1544\ kbit/s\fR , Vol.\ III, Rec.\ G.733. .LP [7] CCITT Recommendation \fIError performance of an international digital\fR \fIconnection forming part of an integrated service digital network\fR , Vol.\ III, Rec.\ G.821. .LP [8] ANSI/IEEE Std 488\(hy1978, \fIIEEE standard digital interface for\fR \fIprogrammable instrumentation\fR . .LP [9] IEC Publication 625 \fIAn interface system for programmable measuring\fR \fIinstruments (byte serial, bit parallel)\fR . .LP [10] ANSI/EIA\(hy232\(hyD\(hy1986 \fIInterface between data terminal equipment\fR \fIand data circuit terminating equipment employing serial binary data\fR \fIinterexchange\fR . \v'2P' .sp 2P .LP \fBRecommendation\ O.171\fR .RT .sp 2P .sp 1P .ce 1000 \fBTIMING JITTER MEASURING EQUIPMENT FOR DIGITAL SYSTEMS\fR .FS See the Supplement\ No.\ 3.8 at the end of this fascicle. .FE .EF '% Fascicle\ IV.4\ \(em\ Rec.\ O.171'' .OF '''Fascicle\ IV.4\ \(em\ Rec.\ O.171 %' .ce 0 .sp 1P .ce 1000 \fI(Geneva, 1980; amended Malaga\(hyTorremolinos, 1984 and Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .LP \fB1\fR \fBIntroduction\fR .sp 1P .RT .sp 2P .LP 1.1 \fIGeneral\fR .sp 1P .RT .PP 1.1.1 The instrumentation specified below will be used to measure timing jitter on digital equipment. This instrumentation, which consists of a jitter measuring circuit and a test signal source, is shown in a general form in Figure\ 1/O.171. While essential requirements are given for the instrumentation, the realization of the equipment configuration is not covered and should be given careful consideration by the designer and user. An error\(hyratio meter may also be required for certain types of measurements. .sp 9p .RT .LP .sp 2 .bp .LP .rs .sp 23P .ad r \fBFigure 1/O.171, p. \fR .sp 1P .RT .ad b .RT .PP 1.1.2 Certain requirements in this specification are provisional and are still under study. These are individually indicated. .PP 1.1.3 It is recommended that Recommendation G.823 [2] be read in conjunction with this Recommendation. .sp 2P .LP 1.2 \fIInterfaces\fR .sp 1P .RT .PP 1.2.1 The instrumentation shall be capable of operating at one or more of the following bit rates and corresponding interface characteristics as described in the appropriate paragraphs of Recommendation\ G.703\ [1]. However, for all bit rates the signal applied to the input of the jitter measuring circuit should be a nominal rectangular pulse. Other signal shapes may produce intersymbol interference thus affecting measurement accuracy. .sp 9p .RT .LP a) \ \ 64 kbits, .FS References to 64\ kbit/s relate to the codirectional interface. Limits for other 64\ kbit/s interfaces are under study. .FE .LP b) 1544 kbit/s, .LP c) 6312 kbit/s, .LP d) 2048 kbit/s, .LP e) 8448 kbit/s, .LP f ) 32 | 64 kbit/s, .LP g) 44 | 36 kbit/s, .LP h) 34 | 68 kbit/s, .LP i) 139 | 64 kbit/s. .PP 1.2.2 As an option the jitter measuring circuit shall be capable of measuring jitter at a clock output port when such an access is provided on digital equipment. .bp .sp 2P .LP 1.3 \fIInterface impedances\fR .sp 1P .RT .PP 1.3.1 The jitter measuring circuit and signal source shall have a return loss better than 20\ dB .FS In the case of 1544\ kbit/s, the signal source shall have the following return loss: 20\ kHz to 500\ kHz \(>=" 14\ dB and 500\ kHz to 1.6\ MHz \(>= 16\ dB. .FE under the conditions listed in Table\ 1/O.171. .sp 9p .RT .ce \fBH.T. [T1.171]\fR .ce TABLE\ 1/O.171 .ce \fBReturn loss test conditions\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(48p) | cw(120p) . Bit rate (kbit/s) Test conditions _ .T& cw(48p) | lw(72p) | lw(48p) . \ \ \ | 64 120 ohms, nonreactive 3 kHz to 300 KHz _ .T& cw(48p) | lw(72p) | lw(48p) . \ \ 1 | 44 100 ohms, nonreactive 20 kHz to 1.6 MHz _ .T& cw(48p) | lw(72p) | lw(48p) . \ \ 2 | 48 75/120/130 ohms, nonreactive 40 kHz to 2.5 MHz _ .T& cw(48p) | lw(72p) | lw(48p) . \ \ 6 | 12 75/110 ohms, nonreactive 100 kHz to 6.5 MHz _ .T& cw(48p) | lw(72p) | lw(48p) . \ \ 8 | 48 75 ohms, nonreactive 100 kHz to 10 MHz _ .T& cw(48p) | lw(72p) | lw(48p) . \ 32 | 64 75 ohms, nonreactive 500 kHz to 40 MHz _ .T& cw(48p) | lw(72p) | lw(48p) . \ 34 | 68 75 ohms, nonreactive 500 kHz to 40 MHz _ .T& cw(48p) | lw(72p) | lw(48p) . \ 44 | 36 75 ohms, nonreactive 500 kHz to 50 MHz _ .T& cw(48p) | lw(72p) | lw(48p) . 139 | 64 75 ohms, nonreactive 7 kHz to 210 MHz _ .TE .nr PS 9 .RT .ad r \fBTable 1/O.171 [T1.171], p. \fR .sp 1P .RT .ad b .RT .LP .sp 3 .sp 2P .LP \fB2\fR \fBTest signal source\fR .sp 1P .RT .PP Tests of digital equipment may be made with either a jittered or a non\(hyjittered digital signal. This will require the pattern generator, clock generator and modulation source shown in Figure\ 1/O.171. .RT .sp 1P .LP 2.1 \fIModulation source\fR .sp 9p .RT .PP The modulation source, testing in conformance with the Series\ G.700 Recommendations, may be provided within the clock generator and/or pattern generator or it may be provided separately. In this Recommendation it is assumed that the modulation source is sinusoidal. .bp .RT .sp 2P .LP 2.2 \fIClock generator\fR .sp 1P .RT .PP 2.2.1 It shall be possible to phase modulate the clock generator from the modulation source and to indicate the peak\(hyto\(hypeak phase deviation of the modulated signal. .sp 9p .RT .PP The generated peak\(hyto\(hypeak jitter and the modulating frequencies shall meet the requirements of Figure\ 2/O.171 and Table\ 2/O.171. .PP 2.2.2 The modulating input sensitivity of the clock generator shall be at least: .LP a) 2 volts peak\(hyto\(hypeak into 600 ohms for bit rates up to and including 8448\ kbit/s, .LP b) 1 volt peak\(hyto\(hypeak into 75 ohms for bit rates up to and including 139 | 64\ kbit/s. .PP 2.2.3 The minimum output of the modulated clock signal and the external timing reference signal shall be 1\ volt peak\(hyto\(hypeak into 75\ ohms. .sp 1P .LP 2.2.4 \fIAccuracy of the clock generator\fR .sp 9p .RT .PP Accuracy requirements are still under study. .RT .sp 1P .LP 2.3 \fIPattern generator\fR .sp 9p .RT .PP The jitter measuring circuit will normally be used with any suitable pattern generator providing the following facilities. .PP \fINote\fR \ \(em\ When test signals are applied to the input of a digital demultiplexer, they must contain the frame alignment signal and justitication control bits. Other measurement techniques are available which do not require the addition of the frame alignment signal or justification control bits. .RT .sp 1P .LP 2.3.1 \fIPatterns\fR .sp 9p .RT .PP The pattern generator shall be capable of providing the following patterns: .PP \fINote\fR \ \(em\ Longer pseudorandom patterns may be necessary for jitter measurements on digital line systems and digital line sections\ [1]. .RT .PP 2.3.1.1 For use at bit rates of 64 kbit/s, a pseudorandom pattern of 2\u1\d\u1\d\ \(em\ 1\ bit length corresponding to Recommendation\ O.152. Encoding in accordance with Recommendation\ G.703\ [1], \(sc\ 1.2.1. .sp 9p .RT .PP 2.3.1.2 For use at bit rates of 1544\ kbit/s 6312\ kbit/s and 44\ 736\ kbit/s, pseudorandom patterns of 2\u1\d\u5\d\ \(em\ 1, 2\u2\d\u0\d\ \(em\ 1, 2\u2\d\u3\d\ \(em\ 1 bit length corresponding to Recommendation\ O.151, \(sc\ 2. .PP \fINote\fR \ \(em\ Definition of the 2\u2\d\u0\d\ \(em\ 1 pseudorandom pattern is under study. .PP 2.3.1.3 For use at bit rates of 2048 kbit/s, 8448 kbit/s and 32\ 064\ kbit/s, a pseudorandom pattern of 2\u1\d\u5\d\ \(em\ 1 length corresponding to Recommendation\ O.151, \(sc\ 2.1. .PP 2.3.1.4 For use at bit rates of 34 | 68 kbit/s and 139 | 64 kbit/s, a pseudorandom pattern of 2\u2\d\u3\d\ \(em\ 1\ bit length corresponding to Recommendation\ O.151, \(sc\ 2.2. .PP 2.3.1.5 For use at all bit rates, a 1000 1000 repetitive pattern. .PP 2.3.1.6 As an option and for use at all bit rates: .LP a) two freely programmable 8\(hybit patterns capable of being alternated at a low rate (e.g.\ from 10\ Hz to 100\ Hz), .LP b) a freely programmable 16\(hybit pattern. .sp 1P .LP 2.3.2 \fIGeneration errors\fR .sp 9p .RT .PP The detailed specification of pattern generator parameters, to be compatible with the jitter measuring circuit specification, is under study. .bp .RT .LP .rs .sp 16P .ad r \fBFigure 2/O.171 p. 12\fR .sp 1P .RT .ad b .RT .ce \fBH.T. [T2.171]\fR .ce TABLE\ 2/O.171 .ce \fBGenerated jitter amplitude versus jitter .ce frequency\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(48p) | cw(72p) | cw(72p) . Bit rate (kbit/s) { A 1: Minimum value of generated jitter from \fIf\fR 0\fR to \fIf\fR 2 } { A 2: Minimum value of generated jitter from \fIf\fR 3 to \fI\fIf\fR 4 } _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ \ | 64 \ 5.0 UI from 2 Hz to 600 Hz 0.5 UI from 6 kHz to 10 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 1 | 44 10.0 UI from 2 Hz to 200 Hz 0.5 UI from 4 kHz to 40 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 2 | 48 10.0 UI from 2 Hz to 2400 Hz 0.5 UI from 45 kHz to 100 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 6 | 12 10.0 UI from 2 Hz to 1600 Hz 0.5 UI from 32 kHz to 160 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 8 | 48 10.0 UI from 2 Hz to 400 Hz { 0.5 UI from 8.5 kHz to 400 kHz } _ .T& cw(48p) | lw(72p) | lw(72p) . \ 32 | 64 10.0 UI from 2 Hz to 1600 Hz 0.5 UI from 32 kHz to 800 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ 34 | 68 10.0 UI from 2 Hz to 1000 Hz 0.5 UI from 20 kHz to 800 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ 44 | 36 16.0 UI from 2 Hz to 3200 Hz { 0.5 UI from 100 kHz to 4500 kHz } _ .T& cw(48p) | lw(72p) | lw(72p) . 139 | 64 10.0 UI from 2 Hz to 500 Hz { 0.5 UI from 10 kHz to 3500 kHz } _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 8 | 48 (low Q) 10.0 UI from 2 Hz to 10.7 kHz { 0.5 UI from 200 kHz to 400 kHz } .TE .LP \fINote 1 to Figure 2/O.171 and Table 2/O.171\fR \ \(em\ Amplitude of jitter specified as peak\(hyto\(hypeak value in unit intervals (UI). .LP \fINote 2 to Figure 2/O.171 and Table 2/O.171\fR \ \(em\ \fIf\fR 1 lies between \fIf\fR 0 and \fIf\fR 2 (see Figure\ 3/O.171 and Table\ 3/O.171). It is not defined here since it is not significant in the context of the requirements of the clock generator. .nr PS 9 .RT .ad r \fBTableau 2/O.171 [T2.171], p. 13\fR .sp 1P .RT .ad b .RT .LP .bp .sp 2P .LP \fB3\fR \fBJitter measuring circuit\fR .sp 1P .RT .sp 1P .LP 3.1 \fIInput sensitivity\fR .sp 9p .RT .PP The jitter measuring circuit is required to operate satisfactorily under the following input conditions: .RT .LP a) The specification for equipment output ports listed in Recommendation\ G.703\ [1]. .LP b) The jitter measuring circuit shall also be capable of measuring at protected test points on digital equipment. Therefore, an additional gain of 30\ dB (40\ dB) shall be provided to compensate for the flat loss at the monitoring points already provided on some equipment. .LP \fINote\ 1\fR \ \(em\ As an option for instrumentation operating at an interface of 1544\ kbit/s the additional gain, where provided, shall be 40\ dB. .LP \fINote\ 2\fR \ \(em\ The influence of the additional gain of 40 dB and of frequency dependent cable loss on the measurement accuracy is under study. .sp 2P .LP 3.2 \fIMeasurement ranges\fR .sp 1P .RT .PP 3.2.1 The jitter measuring circuit shall be capable of measuring peak\(hyto\(hypeak jitter . The measurement ranges to be provided are to be optional but for reasons of compatibility the jitter amplitude/jitter frequency response of the jitter measuring circuit shall meet the requirements of Figure\ 3/O.171 and Table\ 3/O.171 where \fIf\fR\d1\uto \fIf\fR\d4\uare the frequencies defining the jitter frequencies to be measured. .sp 9p .RT .PP 3.2.2 When measuring peak\(hyto\(hypeak jitter it shall also be possible to count the number of occasions and the period of time for which a given selectable threshold of jitter is exceeded. It shall be possible to record these events by means of an external counter, or an internal counter as an option. .PP 3.2.3 It shall be possible to set the threshold of \(sc\ 3.2.2 at any selected measurement value within the measuring range of the jitter measuring circuit. .PP 3.2.4 As an option, the jitter measuring circuit shall be capable of measuring r.m.s. jitter. In such cases it shall be possible to measure 3.0 unit intervals (UI) at jitter frequencies up to \fIf\fR\d2\u, and 0.15\ UI at jitter frequencies from \fIf\fR\d3\uto \fIf\fR\d4\uof Figure\ 3/O.171 and Table\ 3/O.171, the measurement ranges being optional. .PP 3.2.5 Where the option in \(sc 3.2.4 is not provided, the analogue output can be used to make r.m.s. measurements with an external meter. .LP .rs .sp 20P .ad r \fBFigure 3/O.171, p. \fR .sp 1P .RT .ad b .RT .LP .bp .ce \fBH.T. [T3.171]\fR .ce TABLE\ 3/O.171 .ce \fBMeasured jitter amplitude versus jitter frequency\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(48p) | cw(72p) | cw(72p) . Bit rate (kbit/s) { A 1: Maximum value of jitter to be measured from \fIf\fR 1 to \fIf\fR 2 } { A 2: Maximum value of jitter to be measured from \fIf\fR 3 to \fIf\fR 4 } _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ \ | 64 \ 5.0 UI from 20 Hz to 600 Hz 0.5 UI from 6 kHz to 10 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 1 | 44 10.0 UI from 10 Hz to 200 Hz 0.3 UI from 7 kHz to 40 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 2 | 48 10.0 UI from 20 Hz to 2400 Hz 0.5 UI from 45 kHz to 100 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 6 | 12 10.0 UI from 10 Hz to 1600 Hz 0.5 UI from 32 kHz to 160 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 8 | 48 10.0 UI from 20 Hz to 400 Hz { 0.5 UI from 8.5 kHz to 400 kHz } _ .T& cw(48p) | lw(72p) | lw(72p) . \ 32 | 64 10.0 UI from 60 Hz to 1600 Hz 0.5 UI from 32 kHz to 800 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ 34 | 68 { 10.0 UI from 100 Hz to 1000 Hz } 0.5 UI from 20 kHz to 800 kHz _ .T& cw(48p) | lw(72p) | lw(72p) . \ 44 | 36 16.0 UI from 10 Hz to 3200 Hz { 0.5 UI from 100 kHz to 4500 kHz } _ .T& cw(48p) | lw(72p) | lw(72p) . 139 | 64 10.0 UI from 200 Hz to 500 Hz { 0.5 UI from 10 kHz to 3500 kHz } _ .T& cw(48p) | lw(72p) | lw(72p) . \ \ 8 | 48 (low Q) { 10.0 UI from 20 Hz to 10.7 kHz } 0.5 UI from 200 kHz to 400 kHz .TE .LP \fINote to Figure 3/O.171 and Table 3/O.171\fR \ \(em\ Amplitude of jitter specified as peak\(hyto\(hypeak value in unit intervals (UI). .nr PS 9 .RT .ad r \fBTable 3/O.171 [T3.171], p. \fR .sp 1P .RT .ad b .RT .LP .sp 1 .sp 2P .LP 3.3 \fIMeasurement bandwidths\fR .sp 1P .RT .PP 3.3.1 The basic jitter measuring circuit shall contain filters to limit the band of the jitter frequencies to be measured at the various bit rates. Additional filters shall be provided to further limit the bandwidth for the measurement of specified jitter spectra as defined in the Series\ G.700 Recommendations and for other uses. These additional filters may be either internal or external to the jitter measuring circuit. The filters are to be connected between the phase detector and the measuring device. The bandwidth of the jitter measuring circuit and the filters shall be in accordance with Table\ 4/O.171. .sp 9p .RT .sp 1P .LP 3.3.2 \fIFrequency response of jitter measuring circuit and filters\fR .sp 9p .RT .PP The response of all filters within the passband shall be such that the accuracy requirements of the jitter measuring circuit are met. .PP At frequencies below the lower 3\(hydB point, the attenuation of the highpass filtration shall rise with a value greater than, or equal to, 20\ dB per decade. .PP At frequencies above the upper 3\(hydB point the attenuation of the lowpass filtration shall rise with a value greater than, or equal to, 60\ dB per decade. .PP However, the maximum attenuation of the filters shall be at least 60\ dB. .PP \fINote\fR \ \(em\ The effect of nonsinusoidal jitter on the requirements for the filters is still under study. .bp .RT .ce \fBH.T. [T4.171]\fR .ce TABLE\ 4/O.171 .ce \fBJitter measurement bandwidths and highpass filter cutoff\fR .ce .ce \fBfrequencies\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(36p) | cw(34p) sw(34p) sw(28p) sw(34p) | cw(34p) sw(28p) , ^ | c | c | c | c | c | c. Bit rate (kbit/s) Jitter measurement bandwidth { Point \*`a 3 dB des filtres suppl\*'ementaires } { \fIf\fR 0 (lower 3 dB point) (Hz) } \fIf\fR 1 (Hz) \fIf\fR 4 (kHz) { \fIf\fR 5 (upper 3 dB point) (kHz) } Highpass filter No.\ 1 Highpass filter No.\ 2 _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ \ | 64 2 \ 20 \ \ 10 \(= \ \ 20 \ 20 Hz \ \ 3 kHz _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ 1 | 44 2 \ 10 \ \ 40 \(= \ \ 80 \ 10 Hz \ \ 8 kHz _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ 2 | 48 2 \ 20 \ 100 \(= \ 200 \ 20 Hz 700 Hz \ 18 kHz _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ 6 | 12 2 \ 10 \ 160 \(= \ 320 \ 10 Hz \ 60 Hz \ 24 kHz \ 32 kHz _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ 8 | 48 2 \ 20 \ 400 \(= \ 800 \ 20 Hz \ \ 3 kHz \ 80 kHz _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ 32 | 64 2 \ 60 \ 800 \(= 1600 \ 60 Hz 160 kHz _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ 34 | 68 2 100 \ 800 \(= 1600 100 Hz \ 10 kHz _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ 44 | 36 2 \ 10 4500 \(= 9000 \ 10 Hz 900 kHz _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . 139 | 64 2 200 3500 \(= 7000 200 Hz \ 10 kHz .TE .LP \fINote\ 1\fR \ \(em\ The accuracy of the instrument is specified between frequencies \fIf\fR 1 and \fIf\fR 4. .LP \fINote\ 2\fR \ \(emTwo values are specified for highpass filter No.\ 1 at 6312\ kbit/s and highpass filter No.\ 2 at 2048\ kbit/s, 6312\ kbit/s and 8448\ kbit/s. .nr PS 9 .RT .ad r \fBTable 4/O.171 [T4.171], p. \fR .sp 1P .RT .ad b .RT .sp 2P .LP .sp 4 3.4 \fIMeasurement accuracy\fR .sp 1P .RT .sp 1P .LP 3.4.1 \fIGeneral\fR .sp 9p .RT .PP The measuring accuracy of the jitter measuring circuit is dependent upon several factors such as fixed intrinsic error, frequency response and pattern\(hydepending error of the internal reference timing circuits. In addition there is an error which is a function of the actual reading. .PP The total error at 1\(hykHz jitter frequency (excluding the error due to frequency response) shall be less than .RT .sp 1P .ce 1000 \(+- | % of reading \(+- | \ \(+-\ Y .ce 0 .sp 1P .LP where X is the fixed error of Table\ 5/O.171 and Y an error of 0.01\ UI p\(hyp (0.002\ UI | dr\\d.\\dm\\d.\\ds\\d.\u) which applies if internal timing extraction is used. .bp .sp 1P .LP 3.4.2 \fIFixed error\fR .sp 9p .RT .PP For the system bit rates and for the indicated test sequences the fixed error of the jitter measuring circuit shall be as listed in Table\ 5/O.171 when measured at any jitter frequency between \fIf\fR\d1\uand \fIf\fR\d4\uof Figure\ 3/O.171. .RT .sp 1P .LP 3.4.3 \fIError at other frequencies\fR .sp 9p .RT .PP At jitter frequencies between \fIf\fR\d1\uand \fIf\fR\d4\uother than 1 kHz, the error additional to that defined in \(sc\ 3.4.1 above shall be as listed in Table\ 6/O.171. .PP \fINote\fR \ \(em\ The limits of measuring accuracy of the jitter measuring circuit given in \(sc\ 3.4 are provisional and are still under study. .RT .LP .sp 4 .ce \fBH.T. [T5.171]\fR .ce TABLE\ 5/O.171 .ce \fBFixed error in jitter measurements\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(36p) | cw(34p) sw(34p) sw(28p) sw(34p) sw(34p) sw(28p) , ^ | c s | c | c s ^ | c | c | c | c | c | c. Bit rate (kbit/s) { Jitter in UI for given patterns } 1000 1000 Pseudorandom | ua\d\u)\d All ones or clock input p\(hyp r.m.s. p\(hyp r.m.s. p\(hyp r.m.s. _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ \ | 64 \fB<\fR 0.005 \fB<\fR 0.002 \fB<\fR 0.025 \fB<\fR 0.004 \fB<\fR 0.004 \fB<\fR 0.001 _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ 1 | 44 < 0.005 < 0.002 < 0.025 < 0.004 < 0.004 < 0.001 _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ 2 | 48 < 0.005 < 0.002 < 0.025 < 0.004 < 0.004 < 0.001 _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ 6 | 12 < 0.005 < 0.002 < 0.025 < 0.004 < 0.004 < 0.001 _ .T& cw(36p) | cw(34p) | cw(34p) | cw(28p) | cw(34p) | cw(34p) | cw(28p) . \ \ 8 | 48 < 0.005 < 0.002 < 0.025 < 0.004 < 0.004 < 0.001 _ .TE .nr PS 9 .RT .ad r \fBTableau\ 5/O.171 [T5.171], p. 17\fR .sp 1P .RT .ad b .RT .LP .rs .sp 6P .ad r BLANC .ad b .RT .LP .bp .ce \fBH.T. [T6.171]\fR .ce TABLE\ 6/O.171 .ce \fBFrequency response error\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(36p) | cw(36p) sw(36p) | cw(72p) , ^ | c | c | ^ . Bit rate (kbit/s) Measurement bandwidth { Additional error referring to error at 1\ kHz } \fIf\fR 1 (Hz) \fIf\fR 4 (kHz) _ .T& cw(36p) | cw(36p) | cw(36p) | lw(72p) . \ \ \ | 64 \ 20 \ \ 10 { \(+- | % 20 Hz to 600 Hz \(+- | % 600 Hz to 10 kHz } _ .T& cw(36p) | cw(36p) | cw(36p) | lw(72p) . \ \ 1 | 44 \ 10 \ \ 40 { \(+- | % \fIf\fR 1 to 1 kHz; \(+- 2% to \fIf\fR 4 } _ .T& cw(36p) | cw(36p) | cw(36p) | lw(72p) . \ \ 2 | 48 \ 20 \ 100 { \(+- | % \fIf\fR 1 to \fIf\fR 4 } _ .T& cw(36p) | cw(36p) | cw(36p) | lw(72p) . \ \ 6 | 12 \ 10 \ 160 { \(+- | % \fIf\fR 1 to 1 kHz; \(+- 2% to \fIf\fR 4 } _ .T& cw(36p) | cw(36p) | cw(36p) | lw(72p) . \ \ 8 | 48 \ 20 \ 400 { \(+- 2% \fIf\fR 1 to 300 kHz \(+- 3% 300 Hz to \fIf\fR 4 } _ .T& cw(36p) | cw(36p) | cw(36p) | lw(72p) . \ 32 | 64\fR \ 60\fR \ \ 800\fR \(+- 2% 60 Hz to 300 kHz _ .T& cw(36p) | cw(36p) | cw(36p) | lw(72p) . \ 34 | 68 100 \ 800 { \(+- 3% 300 kHz to \fIf\fR 4 } _ .T& cw(36p) | cw(36p) | cw(36p) | lw(72p) , c | c | c | ^ . \ 44 | 36 \ 10 4500 { \(+- 4% 10 Hz to 200 Hz \(+- 2% 200 Hz to 300 kHz \(+- 3% 300 kHz to 1 MHz \(+- 5% 1 MHz to 3 MHz \(+- 10% > 3 MHz } 139 | 64 200 3500 _ .TE .nr PS 9 .RT .ad r \fBTableau\ 6/O.171 [T6.171], p. 18\fR .sp 1P .RT .ad b .RT .LP .sp 2 .sp 2P .LP 3.5 \fIAdditional facilities\fR .sp 1P .RT .sp 1P .LP 3.5.1 \fIAnalogue output\fR .sp 9p .RT .PP The jitter measuring circuit shall provide an analogue output signal to enable measurements to be made externally to the jitter measuring circuit. .RT .sp 1P .LP 3.5.2 \fIReference timing signal\fR .sp 9p .RT .PP A reference timing signal for the phase detector is required. For end\(hyto\(hyend measurements it may be derived in the jitter measuring circuit from any input pattern. For loop\(hymeasurements it may be derived from a suitable clock source. .RT .sp 2P .LP \fB4\fR \fBOperating environment\fR .sp 1P .RT .PP The electrical performance requirements shall be met when operating at the climatic conditions as specified in Recommendation\ O.3, \(sc\ 2.1. .RT .sp 2P .LP \fBReferences\fR .sp 1P .RT .LP [1] CCITT Recommendation \fIPhysical/electrical characteristics of\fR \fIhierarchical digital interfaces\fR , Vol.\ III, Rec.\ G.703. .LP [2] CCITT Recommendation \fIThe control of jitter and wander within\fR \fIdigital networks which are based on the 2048\ kbit/s hierarchy\fR , Vol.\ III, Rec.\ G.823. .LP .bp