.rs
.\" Troff code generated by TPS Convert from ITU Original Files
.\"                 Not Copyright ( c) 1991 
.\"
.\" Assumes tbl, eqn, MS macros, and lots of luck.
.TA 1c 2c 3c 4c 5c 6c 7c 8c
.ds CH
.ds CF
.EQ
delim @@
.EN
.nr LL 40.5P
.nr ll 40.5P
.nr HM 3P
.nr FM 6P
.nr PO 4P
.nr PD 9p
.po 4P

.rs
\v | 5i'
.ce 1000
APPENDIX\ VI
.ce 0
.ce 1000
(to Recommendation G.961)
.sp 9p
.RT
.ce 0
.ce 1000
\fBBasic access transmission system using SU32 line code\fR 
.sp 1P
.RT
.ce 0
.LP
VI.0
	\fIGeneral\fR 
.sp 1P
.RT
.PP
The SU32 standard will support the full duplex, transparent
transmission of two 64\ kbit/s B\ channels and one 16\ kbit/s D\ channel over
symmetric pair cables using echo cancelling techniques. In addition to
transparent 2B\ +\ D transmission, 5.3\ kbit/s capacity is provided for an
Auxiliary channel supporting data CRC, control, supervisory and maintenance
functions. The bit stream is encoded for transmision using a high performance 
ternary SU32 (substitutional 3B2T) conditional block code, filtered and 
transmitted to line at a baud rate of 108\ kbauds. An orthogonal timing 
signal is superimposed on the line code for symbol sampling; which does 
not compromise either the line code efficiency or performance. A unique 
synchronisation word is used to achieve frame synchronisation. Fast and 
reliable activation is 
ensured by means of a binary handshake procedure, for separate training of
canceller and equaliser.
.RT
.sp 2P
.LP
VI.1
	\fILine code\fR 
.sp 1P
.RT
.PP
The binary data is encoded into a ternary form using the SU32 line code. 
This is based on the fixed and unconditional 3B2T line code and modified 
as follows. Each binary triplet is converted to a ternary duplet and is 
transmitted unless it is identical to the previously transmitted duplet. If
current and previous duplets are identical, then the un\(hyused code word 
\*Q00\*U is transmitted in its place. The SU32 coding rule is shown in 
Table\ VI\(hy1/G.961. In this Table, the left most bit is the first into 
the encoder and the left most symbol the first out of the encoder. 
.RT
.ce
\fBH.T. [T35.961]\fR 
.ce
TABLE\ VI\(hy1/G.961
.ce
\fBSU32 coding (substitutional 3B2T)\fR 
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(42p) | cw(42p) | cw(42p) | cw(42p) .
Binary I/P	Ternary O/P	Binary I/P	Ternary O/P
_
.T&
cw(42p) | cw(42p) | cw(42p) | cw(42p) .
000	\(em\(em	100	\ 0\(em
.T&
cw(42p) | cw(42p) | cw(42p) | cw(42p) .
001	\(em0\ 	101	+\(em
.T&
cw(42p) | cw(42p) | cw(42p) | cw(42p) .
010	\(em+	110	+0\ 
.T&
cw(42p) | cw(42p) | cw(42p) | cw(42p) .
011	\ 0+	111	++  
_
.TE
.nr PS 9
.RT
.ad r
\fBTableau VI\(hy1/G.961 [T35.961], p.\fR 
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
	\fIDecoding\fR 
.sp 9p
.RT
.PP
Decoding of the received signal is the inverse of the coding
process.
.RT
.sp 1P
.LP
	\fITolerance to line polarity inversion\fR 
.sp 9p
.RT
.PP
The code is symmetric so that inversion of the ternary data results in 
an inversion of the decoded binary data. Thus polarity correction due to 
cable inversion can be applied either to scrambled or unscrambled binary 
data, or to ternary data. Both transmitted and received polarity correction 
is 
performed at the NT1.
.RT
.sp 2P
.LP
VI.2
	\fISymbol rate\fR 
.sp 1P
.RT
.PP
The symbol rate is determined by the line code, the bit rate of the information 
stream and the frame structure. The symbol rate is 108\ kbauds. 
.RT
.sp 2P
.LP
VI.2.1\ \ \fIClock tolerance\fR 
.sp 1P
.RT
.sp 1P
.LP
VI.2.1.1\ \ \fINT1 free running clock accuracy\fR 
.sp 9p
.RT
.PP
The tolerance of the NT free running clock shall be \(+- | 92\ ppm.
.bp
.RT
.sp 1P
.LP
VI.2.1.2\ \ \fITolerance of the free running clock in the LT\fR 
.sp 9p
.RT
.PP
The free running clock in the LT will be phase locked to the
exchange clock having a frequency tolerance of \(+- | 0\ ppm thus permitting
operation with any equipment meeting Recommendation\ G.703.
.RT
.sp 2P
.LP
VI.3
	\fIFrame structure\fR 
.sp 1P
.RT
.PP
There are two states of operation of the transmission system,
steady state and training state. The frame structure covered in this section 
is for the steady state (information transfer). 
.PP
The B1, B2, D and CL channels map directly from binary bits through
the scrambler into the ternary frame structure. The SU32 code table is 
designed to exclude certain uniquely identifiable code sequences, which 
are exploited 
for synchronisation purposes.
.RT
.sp 1P
.LP
	\fIMultiframe: Multiframe word and location\fR 
.sp 9p
.RT
.PP
The 12 ms multiframe is identified every 16th 3/4 ms frame by
replacing the CRC data symbol (No.\ 79) with a ternary \*Q0\*U. In all 
other frames, this symbol is binary valued. This, combined with the frame 
synchronisation 
word preceding it, uniquely identifies the position of the start of the
superframe.
.RT
.sp 1P
.LP
	\fIMultiframe Format\fR 
.sp 9p
.RT
.PP
A multiframe consists of sixteen 81\(hyternary\(hysymbol 0.75 ms
frames.
.RT
.LP
.sp 2
.LP
\v'6p'
6 frames of 2B + D
\v'6p'
Frame word
\v'6p'
CRC\d1\u\v'6p'
CL\(hychannel\d1\u6 frames of 2B + D
Frame word
CRC\d2\uCL\(hychannel\d2\u6 frames of 2B + D
Frame word
CRC\d3\uCL\(hychannel\d3\u
.LP
6 frames of 2B + D
Frame word
CRC\d4\uCL\(hychannel\d4\u6 frames of 2B + D
Frame word
CRC\d5\uCL\(hychannel\d5\u6 frames of 2B + D
Frame word
CRC\d6\uCL\(hychannel\d6\u
.LP
6 frames of 2B + D
Frame word
CRC\d7\uCL\(hychannel\d7\u6 frames of 2B + D
Frame word
CRC\d8\uCL\(hychannel\d8\u6 frames of 2B + D
Frame word
CRC\d9\uCL\(hychannel\d1\u
.LP
6 frames of 2B + D
Frame word
CRC\d1\\d0\uCL\(hychannel\d2\u6 frames of 2B + D
Frame word
CRC\d1\\d1\uCL\(hychannel\d3\u6 frames of 2B + D
Frame word
CRC\d1\\d2\uCL\(hychannel\d4\u
.LP
6 frames of 2B + D
Frame word
CRC\d1\\d3\uCL\(hychannel\d5\u6 frames of 2B + D
Frame word
CRC\d1\\d4\uCL\(hychannel\d6\u6 frames of 2B + D
Frame word
CRC\d1\\d5\uCL\(hychannel\d7\u6 frames of 2B + D
Frame word
\*Q0\*U
CL\(hychannel\d8\u
.PP
1\ 
\ 72,\ 73 . |  |  78 . |  |  79 . |  |  80 
\ 81
<--------------------
750 \(*m sec transmission frame
-------------------->
\fB12 ms multiframe structure\fR \fINote\fR \ \(em\ B1, B2, D and CL channel 
data is scrambled. CRC data and frame words are not scrambled. 
.bp
.sp 1P
.LP
VI.3.1\ \ \fIFrame length\fR 
.sp 9p
.RT
.PP
There are 6 (2B\ +\ D) slots in each 3/4 ms 81 symbol frame.
.RT
.sp 1P
.LP
VI.3.2\ \ \fIBinary bit allocation in direction LT to NT\fR 
.sp 9p
.RT
.PP
The following binary bit ordering is applied before
scrambling.
.RT
.ce
\fBH.T. [T36.961]\fR 
.ce

.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
B1 1	B1 2	B1 3	B1 4	B1 4	B1 5	B1 6	B1 7	B1 8	B2 1	B2 2	B2 3	B2 4	B2 5	B2 6	B2 7	B2 8	D 1	D 2
_
.T&
cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
B1 1 \fR	B1 2	B1 3 \fR	B1 4	B1 4 \fR	B1 5 \fR	B1 6	B1 7 \fR	B1 8 \fR	B2 1	B2 2 \fR	B2 3 \fR	B2 4	B2 5 \fR	B2 6 \fR	B2 7 \fR	B2 8 \fR	D 1 \fR	D 2  \fR
_
.T&
cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
B1 1 \fR	B1 2	B1 3 \fR	B1 4	B1 4 \fR	B1 5 \fR	B1 6	B1 7 \fR	B1 8 \fR	B2 1	B2 2 \fR	B2 3 \fR	B2 4	B2 5 \fR	B2 6 \fR	B2 7 \fR	B2 8 \fR	D 1 \fR	D 2  \fR  \fR
_
.T&
cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
B1 1 \fR	B1 2	B1 3 \fR	B1 4	B1 4 \fR	B1 5 \fR	B1 6	B1 7 \fR	B1 8 \fR	B2 1	B2 2 \fR	B2 3 \fR	B2 4	B2 5 \fR	B2 6 \fR	B2 7 \fR	B2 8 \fR	D 1 \fR	D 2  \fR  \fR
_
.T&
cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
B1 1 \fR	B1 2	B1 3 \fR	B1 4	B1 4 \fR	B1 5 \fR	B1 6	B1 7 \fR	B1 8 \fR	B2 1	B2 2 \fR	B2 3 \fR	B2 4	B2 5 \fR	B2 6 \fR	B2 7 \fR	B2 8 \fR	D 1 \fR	D 2  \fR  \fR
_
.T&
cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) | cw(12p) .
B1 1 \fR	B1 2	B1 3 \fR	B1 4	B1 4 \fR	B1 5 \fR	B1 6	B1 7 \fR	B1 8 \fR	B2 1	B2 2 \fR	B2 3 \fR	B2 4	B2 5 \fR	B2 6 \fR	B2 7 \fR	B2 8 \fR	D 1 \fR	D 2
_
.TE
.nr PS 9
.RT
.ad r
\fBTableau [T36.961], p.\fR 
.sp 1P
.RT
.ad b
.RT
.PP
The binary data is scrambled as defined in \(sc\ VI.9 and ternary
encoded. It is then multiplexed into the following frame format.
.ce
\fBH.T. [T37.961]\fR 
.ce

.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) .
T 1	T 2	T 3	T 4	T 5	T 6	T 7	T 8	T 9	T 1 0	T 1 1	T 1 2
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) .
T 1 3	T 1 4	T 1 5	T 1 6\fR	T 1 7	T 1 8	T 1 9	T 2 0	T 2 1	T 2 2	T 2 3	T 2 4
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) .
T 2 5	T 2 6	T 2 7	T 2 8\fR	T 2 9	T 3 0	T 3 1	T 3 2	T 3 3	T 3 4	T 3 5	T 3 6
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) .
T 3 7	T 3 8	T 3 9	T 4 0\fR	T 4 1	T 4 2	T 4 3	T 4 4	T 4 5	T 4 6	T 4 7	T 4 8
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) .
T 4 9	T 5 0	T 5 1	T 5 2\fR	T 5 3	T 5 4	T 5 5	T 5 6	T 5 7	T 5 8	T 5 9	T 6 0
_
.T&
cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) .
T 6 1	T 6 2	T 6 3	T 6 4\fR	T 6 5	T 6 6	T 6 7	T 6 8	T 6 9	T 7 0	T 7 1	T 7 2
_
.TE
.nr PS 9
.RT
.ad r
\fBTableau [T37.961], p.\fR 
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
VI.3.3\ \ \fIBinary bit allocation in direction NT1 to LT\fR 
.sp 9p
.RT
.PP
The frame structure and order of bits in the NT1 to LT direction is to 
identical that used in the LT to NT1 direction specified in \(sc\ VI.3.2 
above.
.RT
.sp 2P
.LP
VI.4
	\fIFrame word\fR 
.sp 1P
.RT
.PP
The frame word of six ternary zeros terminated by the binary
CRC\d1\\d5\ubit (as illustrated in the above Table) is used to define the 
0.75\ ms frame 
boundaries. Note that once every superframe a ternary zero is substituted 
for the binary CRC check bit. This frame word is unique and cannot be emulated 
by any 2B\ +\ D data pattern. 
.PP
The frame word specified above is the same in both directions of
transmission.
.bp
.RT
.sp 2P
.LP
VI.5
	\fIFrame alignment procedure\fR 
.sp 1P
.RT
.PP
The frame alignment function is specified in the Activation
sequence. 2B\ +\ D transmission cannot commence unless frame alignment 
has been achieved. Initial frame alignment is considered to have been achieved 
when the cumulative total of correct versus incorrectly received 7\(hybit 
frame words 
exceeds\ 4. In steady state operation, this cumulative count is maintained 
but limited to a maximum of\ 64. Frame alignment loss is flagged if this 
cumulative total falls below two. 
.RT
.sp 2P
.LP
VI.6
	\fIMultiframe\fR 
.sp 1P
.RT
.PP
The multiframe structure has been described in the frame structure, \(sc\ 
VI.3 of this Appendix. 
.RT
.sp 2P
.LP
VI.7
	\fIFrame offset between LT\(hyNT1 and NT1\(hyLT frames\fR 
.sp 1P
.RT
.PP
No specific phase requirements are necessary between frames in the LT\(hyNT1 
and NT1\(hyLT directions. 
.RT
.sp 2P
.LP
VI.8
	\fICL channel\fR 
.sp 1P
.RT
.PP
An embedded protected operations channel (EPOC) of 4\ kbit/s is
partially allocated to supervisory and maintenance functions. Significant 
spare capacity and undefined bits remain for both future allocation of 
messages as 
well as specific national requirements.
.PP
This channel is protected by a 6\(hybit CRC check and compelled protocol 
which provides that all messages are repeated every 6\ ms. 
.RT
.sp 1P
.LP
VI.8.1\ \ \fIBit rate\fR 
.sp 9p
.RT
.PP
Twenty\(hyfour bits per 6 ms multiframe (4 kbit/s) are allocated to an 
embedded protected operations channel (EPOC). This supports supervisory 
and 
maintenance functions between the network and the NT1 and includes spare
capacity for user defined functions. Additionally a further 1.33\ kbit/s is
allocated to provide an error detecting CRC15 and 12\ ms framing to the
CL\ channel.
.RT
.sp 1P
.LP
VI.8.2\ \ \fIStructure\fR 
.sp 9p
.RT
.PP
Within each 12 frame, the operations channel sends two consecutive messages 
of 24\ bits. Each 24\ bit message comprises: 
.RT
.LP
	\(em
	1\ bit
	Ready for data/data valid (R).
.LP
	\(em
	5\(hybit
	Maintenance channel (M).
.LP
	\(em
	9\(hybit
	Supervisory channel (S).
.LP
	\(em
	3
	Unassigned bits (500 bit/s subsidiary channel).
.LP
	\(em
	6\(hybit
	Cyclic redundancy check field (CRC).
.PP
The structure of the CL channel is as follows:
.LP
.sp 2
.ce
\fBH.T. [T38.961]\fR 
.ce

.ps 9
.vs 11
.nr VS 11
.nr PS 9
.ce
Unable to convert table
.nr PS 9
.RT
.ad r
\fBTableau [T38.961], p.3\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.sp 2
.bp
.sp 1P
.LP
VI.8.2.1\ \ \fIMaintenance messages\fR 
.sp 9p
.RT
.PP
In the ET to NT1 direction 9 of the 32 possible command messages
are allocated. An identical message is returned in the NT1 to ET direction 
as an acknowledgement. 
.RT
.LP
\fIET to NT1 maintenance message codes\fR No.
Message
5\(hybit code
M1
M2
M3
M4
M5
.LP
1
No loopback (null message)/remove loopback
1
1
1
1
1
2
Provide loopback B1 at NT1
1
1
0
1
1
.LP
3
Provide loopback B2 at NT1
1
0
1
1
1
4
Provide loopback B1 + B2 at NT1
1
0
0
1
1
.LP
5
Provide loopback B1 + B2 + D at NT1
1
0
0
0
1
6
Provide loopback B1 at regenerator
0
0
1
1
1
.LP
7
Provide loopback B2 at regenerator
0
1
0
1
1
8
Provide loopback B1 + B2 at regenerator
0
1
1
1
1
.LP
9
Provide loopback B1 + B2 + D loopback at regenerator
0
1
1
0
1
.sp 1P
.LP
	\fISupervisory sub\(hychannel message formats\fR 
.sp 9p
.RT
.PP
A 9\(hybit field is available in each direction of transmission to
allow supervisory information to be provided. This contains an 8\(hybit
data/address field and a one\(hybit flag used to indicate whether or not 
the 8\(hybit field contains valid data. 
.RT
.LP
\fIET to NT1 supervisory message command codes\fR 
.LP
No
Supervisory message and destination
S\(hyinterface
\ 1
No supervisory information requested
1\ 1111\ 1111
\ 2
ET AGC value
0\ 0000\ 0100
\ 3
ET eye closure
0\ 0000\ 0101
.LP
\ 4
ET eye height
0\ 0000\ 0110
\ 5
ET CRC error count
0\ 0000\ 0111
\ 6
NT1 AGC value
0\ 0001\ 0000
\ 7
NT1 Eye closure
0\ 0001\ 0001
.LP
\ 8
NT1 Eye height
0\ 0001\ 0010
\ 9
NT1 CRC error count
0\ 0001\ 0011
11
Regenerator LT\(hyside receiver AGC
0\ 0000\ 1000
12
Regenerator LT\(hyside receiver Eye closure
0\ 0000\ 1001
.LP
13
Regenerator LT\(hyside receiver Eye height
0\ 0000\ 1010
14
Regenerator LT\(hyside receiver CRC count
0\ 0000\ 1011
15
Regenerator NT1\(hyside receiver AGC
0\ 0000\ 1100
16
Regenerator NT1\(hyside receiver Eye closure
0\ 0000\ 1101
.LP
17
Regenerator NT1\(hyside receiver Eye height
0\ 0000\ 1110
18
Regenerator NT1\(hyside CRC count
0\ 0000\ 1111
.bp
.sp 1P
.LP
VI.8.3\ \ \fIProtocols and procedures\fR 
.sp 9p
.RT
.PP
The maintenance channel is used to set loop backs from the LT. When a maintenance 
message has been received free from error and implemented, the 
same message is echoed back from the NT1 to the LT.
.PP
The supervisory channel is designed to be used as a compelled system, with 
a command sent by the LT end until the expected response is received. A 
delimiting idle message of nine ONEs is employed. All valid messages and
responses set the first bit of the 9\ supervisory bits to a ONE. An 8\ 
bit word can therefore be securely passed across this channel. An example 
use of the 
supervision channel is for reporting eye closure information from the NT1 to
the\ LT.
.RT
.sp 1P
.LP
VI.8.4\ \ \fICL channel performance\fR 
.sp 9p
.RT
.PP
With a mean 144 kbit/s error rate of 1 in 1000, characterised by a mean 
error burst size of\ 10, the following performance will be 
achieved:
.RT
.LP
	a)
	99.8% of all messages will be conveyed within 6 ms.
.LP
	b)
	No more than one message per hour shall be conveyed in more
than 18\ ms.
.LP
	c)
	The mean erroneous error message rate is less than one per
hour with a maximum time to correction of 18\ ms.
.sp 2P
.LP
VI.9
	\fIScrambling\fR 
.sp 1P
.RT
.PP
B1, B2, D and C channel binary data is scrambled as
follows:
.RT
.LP
	a)
	NT to LT scrambler polynomial
\v'6p'
.sp 1P
.ce 1000
1 
\o'\(ci+' \fIx\fR \uD\dlF261\u1\d\u8\d 
\o'\(ci+' \fIx\fR \uD\dlF261\u2\d\u3\d (where 
\o'\(ci+' denotes exclusive OR)
.ce 0
.sp 1P
.LP
.sp 1
	b)
	LT to NT scrambler polynomial
\v'6p'
.sp 1P
.ce 1000
1 
\o'\(ci+' \fIx\fR \uD\dlF261\u5\d 
\o'\(ci+' \fIx\fR \uD\dlF261\u2\d\u3\d
.ce 0
.sp 1P
.sp 2P
.LP
.sp 1
VI.10\ \ 
\fIActivation/deactivation\fR 
.sp 1P
.RT
.sp 1P
.LP
VI.10.1\ \ \fISignals used for activation\fR 
.sp 9p
.RT
.PP
Figure VI\(hy1/G.961 illustrates the activation sequence initiated by the 
ET in terms of function elements (FE) and INFO's. 
.RT
.PP
Figure VI\(hy2/G.961 illustrates the activation sequence initiated
by the user in terms of function elements (FE) and INFO's.
.LP
.rs
.sp 10P
.LP
.bp
.LP
.rs
.sp 47P
.ad r
\fBFigure VI\(hy1/G.961, (N), p.4\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.LP
.rs
.sp 47P
.ad r
\fBFigure VI\(hy2/G.961, (N), p.5\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.PP
The definition of the function elements, LT states and NT states used in 
the activation Figures and the state transition tables in this Appendix 
is as follows. 
.LP
.sp 2
.LP
\fBDefinition of FE's LT's and NT's\fR Function elements (FE)
FE1
Activation request for the interface from the ET.
FE2
Line signal detected on the digital section.
.LP
FE3
The digital section is activated (in synchronisation).
FE4
The user network at the T reference point is activated or a loopback
is operated.
FE5
Deactivation request for the digital section.
FE6
The digital section and the interface at the T reference point has
been de\(hyactivated.
FE7
Error indication. (Loss of synchronisation or no line signal
detect).
.LP
NT1 states
NT1
The NT1 is ready for activation.
NT2
The NT1 is executing the digital section training sequence.
NT3
The NT1 is in synchronisation with the LT and the LT to NT1 digital
section is capable of error free data transmission.
NT4
Equivalent to state NT3 plus synchronisation of the interface at
the T\(hyreference point.
.LP
NT5
The 2B + D data channel through the digital section and across the
T\ reference point is fully operational.
NT6
The NT1 has sent an activate request to the LT and is waiting for a
response.
NT7
The NT1 is not active but is not ready for activation.
.LP
LT states
LT1
The LT is ready for activation.
LT2
The LT is executing the digital section training sequence.
LT3
The digital section has been correctly activated and is synchronised
in both directions.
LT4
Both the digital section and the interface at the T reference point are
correctly activated and synchronised.
.LP
LT5
The 2B + D data channel through the digital section and across the
T\ reference point is fully operational.
LT7
The LT has ceased transmission over the digital section and is waiting for
all line signals to disappear.
.PP
The response of the digital section to the activation request FE1 from 
the ET or the activation request INFO\ 1 from the TE is to signal across 
the digital section by the transmission of a quarter baud rate (27\ kHz) 
wake\(hyup tone. 
.PP
In the NT1 to LT direction, the duration of this wake up tone shall
not be less than 32\ complete cycles of the repetitive data pattern\ +\(hy\(hy+. 
The 
tone shall not exceed 10\ ms in duration.
.PP
In the LT to NT1 direction, the duration of the wake\(hyup tone shall not 
be less than 32\ complete cycles of the repetitive data pattern\ +\(hy\(hy+. 
The tone shall not exceed 10\ ms in duration. 
.bp
.RT
.sp 1P
.LP
VI.10.2\ \ \fIDefinition of internal timers\fR 
.sp 9p
.RT
.PP
The activation procedure shall nominally take 120\ ms to the point where 
error free framed transmission can commence. 
.PP
In the event of the activation procedure failing, or loss of
synchronisation on either the interface at the T\(hyReference point or on the
transmission system described herein, a timer is required in the NT to
terminate operation. This timer shall not exceed 65\ ms measured from the 
point of loss of synchronisation; or in the case of activation, measured 
from the 
time at which synchronisation should be achieved.
.PP
It is not essential to employ a timer for the identification of
failure to activate or loss of synchronisation signalled to the LT. However,
where there is no external control of the de\(hyactivation procedure applied to
the two wire LT termination, a timer not exceeding 65\ ms from the time 
of loss of synchronisation or as measured from the time at which activation 
should have been achieved should be employed. 
.RT
.sp 1P
.LP
VI.10.3\ \ \fIActivation procedure\fR 
.sp 9p
.RT
.PP
Table VI\(hy2/G.961 shows the training sequence signals that should be 
transmitted to line by the LT and NT1. At the LT, offsets are measured 
in baud periods from the end of the wake\(hyup tone transmission. At the 
NT1, offsets are measured in baud periods from the detection of the end 
of the wake\(hyup tone. For correct operation, it is necessary that the 
time from the LT completing the 
wake\(hyup tone burst, to the NT1 detecting the end of wake\(hyup tone 
is less than or equal to 32\ bauds. 
.RT
.ce
\fBH.T. [T39.961]\fR 
.ce
TABLE\ VI\(hy2/G.961
.ce
\fBActivation training sequence\fR 
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(40p) | cw(40p) | cw(34p) | cw(40p) | cw(40p) | cw(34p) .
Offset  (bauds)	Duration  (bauds)	LT timing signal 	LT data 	NT timing signal 	NT data 
_
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
\ \  |  \ 0	\ \ 64	OFF	None	OFF	None
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
\ \  |  64	\ 512	ON	None	OFF	None
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
\ \  | 76	\ 512	OFF	None	ON	None
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
\ 1 | 88	\ 512	ON	None	OFF	None 
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
\ 1 | 00	\ 512	OFF	None	ON	None
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
\ 2 | 12	4096	ON	PRBS	OFF	None 
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
\ 6 | 08	\ \ 32	ON	None	OFF	None
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
\ 6 | 40	4064	ON	None	OFF	PRBS
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
10 | 04	(405) (Note\ 1)	ON	Ternary  (Note\ 1)	OFF	None
.T&
cw(40p) | cw(40p) | lw(34p) | cw(40p) | lw(40p) | cw(34p) .
10 | 09 (Note\ 1)	(405) (Note\ 2)	ON	Ternary  (Note\ 2)	OFF	Ternary (Note\ 2)
.TE
.LP
PRBS
stand for a 511\ bit pseudo\(hyrandom binary sequence generated by
the polynomial (1\ 
\o'\(ci+'\ \fIx\fR
\uD\dlF261\u4\d\ 
\o'\(ci+'\ \fIx\fR
\uD\dlF261\u9\d).
.LP
\fINote\ 1\fR
\ \(em\ The transmission of ternary data from the LT to the NT1 from this
time onwards in continuous. The NT1 will not return ternary data until it has achieved synchronisation, the figure of 405 bauds and the subsequent offset
to the next row is intended as a guide to the normal duration for this
process.
.LP
\fINote\ 2\fR
\ \(em\ Ternary transmission from NT1 to LT implies that error\(hyfree
transmission and frame synchronisation have been achieved in the NT. Following the LT acquiring synchronisation, full duplex 2B |  |  transmission can
commence.
.nr PS 9
.RT
.ad r
\fBTableau VI\(hy2/G.961 [T39.961], p\fR 
.sp 1P
.RT
.ad b
.RT
.PP
The conditional step between the NT1 acquiring synchronisation and returning 
ternary data is included to provide a mechanism by which the optional alignment 
of LT to NT1 and NT1 to LT frame words can be achieved. 
.bp
.sp 1P
.LP
VI.10.4\ \ \fIState transition table of the NT\fR 
.sp 9p
.RT
.PP
See Table VI\(hy3/G.961.
.RT
.ce
\fBH.T. [T40.961]\fR 
.ce
TABLE\ VI\(hy3/G.961
.ce
\fBState transition table of the NT\fR 
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
lw(18p) | cw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | cw(21p) .
	State  	NT1 ready for act.	NT2 training 	NT3 wait for T	NT4 wait for  data valid 	NT5 steady state 	NT6 TE act. 	NT7 pending deact.  
_
.T&
lw(18p) | cw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | cw(21p) .
	Signal transmitted   to TE	I0	I0	I2	I2	I4	I0	
_
.T&
cw(51p) | lw(27p) | lw(27p) | lw(21p) | lw(27p) | lw(27p) | lw(27p) | lw(21p) .
Events							
_
.T&
lw(18p) | lw(33p) | lw(27p) | lw(27p) | lw(21p) | lw(27p) | lw(27p) | lw(27p) | lw(21p) .
Source	Event							
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | cw(21p) .
LT	Activate indication [FE1]	NT2	\(em	\(em	\(em	\(em	NT2	\(em
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | cw(21p) .
NT1	In synch. [FE3]	/	NT3	\(em	\(em	\(em	/	\(em
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | cw(21p) .
TE	INFO 3	/	/	NT4	\(em	\(em	/	\(em
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | cw(21p) .
NT1	Data valid	/	/	/	NT5	\(em	/	\(em
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | cw(21p) .
TE	Activate indication INFO 1	NT6	/	/	/	/	/	\(em 
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | cw(21p) .
NT1	Loss of synch. [FE3]	\(em	NT7	NT7	NT7	NT7	\(em	\(em
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | cw(21p) .
NT1	No line sig. detect on DS	\(em	\(em	\(em	\(em	\(em	\(em	NT1
.TE
.LP
\(em
No change 
.LP
/
Impossible
.LP
[ | 
Remote source event
.LP
DS
Digital system 
.nr PS 9
.RT
.ad r
\fBTableau VI\(hy3/G.961 [T40.961], p.\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.sp 12
.bp
.sp 1P
.LP
VI.10.5\ \ \fIState transition table of the LT\fR 
.sp 9p
.RT
.PP
See Table VI\(hy4/G.961.
.RT
.ce
\fBH.T. [T41.961]\fR 
.ce
TABLE\ VI\(hy4/G.961
.ce
\fBState transition table of the LT 
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
lw(18p) | cw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | lw(21p) .
	State   	LT1 Ready  for act.	LT2 Training	LT3 Dig. sect. active	LT4 T\(hyref in synch.	LT5 Steady state	LT7 Pending deact.  	
_
.T&
lw(18p) | cw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | cw(27p) | lw(21p) .
	Signal  transmitted  to DS	Inactive	Training seq.	Steady state	Steady state	Steady state	Inactive	
_
.T&
cw(51p) | lw(27p) | lw(27p) | lw(21p) | lw(27p) | lw(27p) | lw(27p) | lw(21p) .
Events							
_
.T&
lw(18p) | lw(33p) | lw(27p) | lw(27p) | lw(21p) | lw(27p) | lw(27p) | lw(27p) | lw(21p) .
Source	Event							
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | cw(21p) .
ET	FE1	LT2	/	/	/	/		\(em
.T&
lw(51p) | lw(177p) .
(activate reqst.)	
_
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | cw(21p) .
LT	DS  in\(hysynch.	/	FE3  LT3	\(em	\(em	\(em		/
_
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | cw(21p) .
LT	FE2	/						
.T&
lw(51p) | lw(177p) .
No line activity	
.T&
lw(51p) | lw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | cw(21p) .
LSD  > False		\(em	\(em	\(em	\(em		LT1
_
.T&
lw(18p) | lw(33p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | cw(21p) .
NT1	[INFO 3]	/	/	FE4	\(em	\(em		/
.T&
lw(51p) | lw(27p) | lw(27p) | cw(21p) | lw(27p) | lw(27p) | lw(27p) | lw(21p) .
Ready for data			LT4				
_
.T&
lw(18p) | lw(33p) | lw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | lw(21p) .
LT			FE7	FE7	FE7	FE7 		
.T&
lw(51p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | cw(21p) .
DS loss of synchronisation	/	LT7	LT7	LT7	LT7		\(em
_
.T&
lw(18p) | lw(33p) | lw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | lw(21p) .
ET	FE5		FE7	FE7	FE7	FE7 		
.T&
lw(51p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | cw(21p) .
deactivation request	/	LT7	LT7	LT7	LT7		\(em
_
.T&
lw(51p) | cw(27p) | cw(27p) | cw(21p) | cw(27p) | cw(27p) | lw(27p) | cw(21p) .
ET  Data valid	/	/	/	LT5	\(em		\(em
.TE
.LP
\(em
No change
.LP
/
Impossible
.LP
[ | 
Remote source event 
.LP
LSD
Line signal detect 
.nr PS 9
.RT
.ad r
\fBTableau VI\(hy4/G.961 [T41.961], p.\fR 
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
VI.10.6\ \ \fIActivation times\fR 
.sp 9p
.RT
.PP
The \*Qcold start\*U and \*Qwarm start\*U times will be 120 ms\(+- | 0\ 
ms with all cable combinations permissible. This reliable and repeatable 
activation 
time is a result of the specific activation sequence specified in this SU32
standard.
.bp
.RT
.sp 2P
.LP
VI.11\ \ \fIJitter\fR 
.sp 1P
.RT
.PP
Jitter performance must be sufficient for the purpose of providing the 
clock for interface at the T\(hyreference point transmission function in 
accordance with Recommendation\ I.430.
.PP
The SU32 proposal features an orthogonal timing signal superimposed on 
the data. This leads to stable and low jitter digital phase locked loop 
timing circuitry being easily achieved. 
.RT
.sp 1P
.LP
VI.11.1 to V1.11.3
.sp 9p
.RT
.PP
For further study.
.RT
.sp 2P
.LP
VI.12\ \ \fITransmitter output characteristic of the NT or LT\fR 
.sp 1P
.RT
.sp 1P
.LP
VI.12.1\ \ \fIPulse amplitude\fR 
.sp 9p
.RT
.PP
The nominal pulse amplitude shall be zero to peak 1.8 volts. The
tolerance on this peak pulse amplitude shall be such that signal power and
amplitude vs. frequency spectrum performance is as specified
in\ \(sc\ VI.12.
.RT
.sp 1P
.LP
VI.12.2\ \ \fIPulse shape\fR 
.sp 9p
.RT
.PP
The pulse shape is determined by the pulse mask of
Figure\ VI\(hy3/G.961.
.RT
.LP
.rs
.sp 26P
.ad r
\fBFigure VI\(hy3/G.961, (N), p.\fR 
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
VI.12.4\ \ \fIPower spectrum\fR 
.sp 9p
.RT
.PP
SU32 has a code spectrum modified by the conditional coding rule
compared to random ternary signalling. The theoretical power spectrum when
using SU32 having full width rectangular pulse shaping with transformer
coupling is given in Figure\ VI\(hy4/G.961.
.PP
Limits for the transmitted power spectral density are given in
Figure\ VI\(hy5/G.961.
.bp
.RT
.LP
.rs
.sp 27P
.ad r
\fBFigure VI\(hy4/G.961, (N), p.10\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.rs
.sp 21P
.ad r
\fBFigure VI\(hy5/G.961, (N), p.11\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.sp 1P
.LP
	\fIPower levels\fR 
.sp 9p
.RT
.PP
Signals sent to line must conform to the following criteria, under all 
operating conditions with 140\ ohms resistive termination: 
.RT
.LP
	a)
	The maximum total transmit power, averaged in any 1\ second
period must not exceed +11\ dBm.
.LP
	b)
	The maximum transmit power average in any 1 second period in
any 3\ kHz band, below 100\ kHz, must be less than 0\ dBm. This
limit extends down to DC (excluding power feed).
.LP
	c)
	The nominal recommended transmit power will be +9.5\ dBm with
a tolerance of \(+- | \ dB.
.sp 2P
.LP
VI.13\ \ \fITransmitter/receiver termination\fR 
.sp 1P
.RT
.sp 1P
.LP
VI.13.1\ \ \fIImpedance\fR 
.sp 9p
.RT
.PP
The nominal output/input impedance looking towards the NT shall be 140\ 
ohms. The nominal output/input impedance looking towards the LT shall be 
140\ ohms.
.RT
.sp 1P
.LP
VI.13.2\ \ \fIReturn loss\fR 
.sp 9p
.RT
.PP
For further study.
.RT
.sp 1P
.LP
VI.13.3\ \ \fILongitudinal conversion loss\fR 
.sp 9p
.RT
.PP
The longitudinal conversion loss in the range 100\ Hz to 1.6\ times the 
symbol rate (fO) shall exceed 46\ dB. For a frequency 
10\ MHz\ >\ \fIf\fR \ >\ 1.6\ \fIf\fR\d0\u,
the longitudinal loss shall exceed 46 \(em 40\ log (
\fIf\fR /1.6\ \fIf\fR\d0\u) dB or 24\ dB whichever is greater.
\v'2P'
.RT
.sp 2P
.LP
\fBSupplement\ No.\ 15\fR 
.RT
.sp 2P
.sp 1P
.ce 1000
\fBALMOST\(hyDIFFERENTIAL\ QUASI\(hyTERNARY\ CODE\ (ADQ\ CODE)\fR 
.EF '%	Fascicle\ III.5\ \(em\ Suppl.\ No.\ 15''
.OF '''Fascicle\ III.5\ \(em\ Suppl.\ No.\ 15	%'
.ce 0
.sp 1P
.ce 1000
(Referred to in Recommendation G.911, this Supplement is to be found on 
page 673 
.sp 9p
.RT
.ce 0
.sp 1P
.ce 1000
of Fascicle III.3 of the Orange Book, Geneva, 1977)
\v'2P'
.ce 0
.sp 1P
.sp 2P
.LP
\fBSupplement\ No.\ 27\fR 
.RT
.sp 2P
.sp 1P
.ce 1000
\fBINTERFERENCE\ FROM\ EXTERNAL\ SOURCES\fR 
.EF '%	Fascicle\ III.5\ \(em\ Suppl.\ No.\ 27''
.OF '''Fascicle\ III.5\ \(em\ Suppl.\ No.\ 27	%'
.ce 0
.sp 1P
.ce 1000
(Referred to in Recommendations G.221 and G.950;
this Supplement is to be found on page 346
.sp 9p
.RT
.ce 0
.LP
of Fascicle III.2 or on page 390 of Fascicle III.3 of the Red Book, Geneva, 
1985.) 
.bp
.sp 1P
.ce 1000
.ce 0
.sp 1P
.sp 2P
.LP
\fBSupplement\ No.\ 34\fR 
.RT
.sp 2P
.sp 1P
.ce 1000
\fBTEMPERATURE\ IN\ UNDERGROUND\ CONTAINERS\ FOR\ THE\ INSTALLATION |
OF\ REPEATERS\fR 
.EF '%	Fascicle\ III.5\ \(em\ Suppl.\ No.\ 34''
.OF '''Fascicle\ III.5\ \(em\ Suppl.\ No.\ 34	%'
.ce 0
.sp 1P
.ce 1000
\fI(Melbourne, 1988)\fR 
.sp 9p
.RT
.ce 0
.sp 1P
.ce 1000
(see Recommendation G.950)
.sp 9p
.RT
.ce 0
.sp 1P
.LP
\fB1\fR 	\fBGeneral\fR 
.sp 1P
.RT
.PP
This Supplement consists of two parts: A and B.
.PP
\fIPart A\fR  | (source: Federal Republic of Germany) informs about the
ground temperature taken from meteorological sources in most regions of the
world, and shows the seasonal variations as a function of the depth (in the
Federal Republic of Germany).
.PP
\fIPart B\fR  | (source: Italy) gives guidelines for the calculation of 
the ground temperature in the container, depending, \fIinter alia\fR , 
from the 
atmospheric temperature, the depth and the dissipation of the equipment 
in the container. 
.PP
Both parts give additionally some general information which is useful as 
a guidance for planning. 
.RT
.sp 2P
.LP
\fB2\fR 	\fBPart A\fR 
.sp 1P
.RT
.sp 1P
.LP
2.1
	\fIDefinition\fR 
.sp 9p
.RT
.PP
In the following, climatic conditions are discussed which are
relevant to small underground containers without any means for adjusting to
specific temperature conditions. These containers are normally hermetically
closed and need not be opened e.g., for preventive maintenance. They can be
operated with or without gas pressure supervision or they may contain drying
agents.
.RT
.sp 1P
.LP
2.2
	\fITemperature in underground containers\fR 
.sp 9p
.RT
.PP
The temperature in underground containers depends on the
temperature of the surrounding soil. Additionally, it is influenced by the
power dissipation of the installed equipment.
.PP
The ground temperature at various depths is well known for most of the 
regions of the world [1]. Figure\ 1 shows the seasonal variation of the 
ground temperature as a function of the long term mean value of the ground 
temperature. Examples of the variation of the temperature with time for a
period of 1\ year is shown in Figure\ 2. The yearly minimum and maximum
temperatures as a function of the depth are plotted in Figure\ 3. Figures\ 2
and\ 3 are examples only for a specific region in Germany (Federal Republic 
of) and for sandy soil. 
.RT
.LP
.rs
.sp 16P
.ad r
\fBFigure 1, (N), p.12\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.LP
.rs
.sp 27P
.ad r
\fBFigure 2, (N), p.13\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.rs
.sp 21P
.ad r
\fBFigure 3, (N), p.14\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.PP
The composition of the soil has a significant effect on the
temperature and its variation with time. It should be noted that this variation 
occurs slowly, depending on the composition of the soil and on the depth. 
.PP
The mean value of the temperature in the container is the same as that 
of the ground, if the possible increase caused by the heat generated by 
the 
power dissipation of the equipment is neglected. Variations of the air
temperature cause variations of the temperature in the container, but with a
time delay, and with an attenuation of the amplitude depending on the design 
of the container. 
.RT
.sp 1P
.LP
2.3
	\fIConclusion\fR 
.sp 9p
.RT
.PP
The temperature in small underground containers e.g., for the
installation of remote power\(hyfed repeaters depends on the geographical 
region, the composition of the soil, the depth of installation and the 
power 
dissipation of the installed equipment.
.PP
The humidity within the container is independent of external
influences and can be controlled by suitable means, if necessary.
.RT
.sp 2P
.LP
\fB3\fR 	\fBPart B\fR 
.sp 1P
.RT
.sp 1P
.LP
3.1
	\fITemperature in underground housing containing high dissipation\fR 
\fIequipment\fR 
.sp 9p
.RT
.PP
The temperature in the underground housing depends on the
temperature of the surrounding soil, its composition and on the amount 
of power dissipated in the equipment. 
.RT
.PP
3.1.1
The temperature in the soil at different depths can be directly
measured at the site or can be calculated from seasonal mean temperature 
of the site (at ground level) taking into account thermal resistivity and 
diffusity of the soil. 
.PP
Short term variations, like daily excursions, are rapidly damped and become 
negligible at a depth greater than 0.3\ m so that only seasonal 
variation diffuses farther in the ground.
.PP
Of course such variations too are attenuated and delayed following the 
depth and the soil composition. 
.RT
.PP
3.1.2
The heat generated by equipment dissipation in the housing is
transferred via housing walls into surrounding soil thus disturbing the
existing temperature field and determining a local gradient which decreases
with the distance from housing walls.
.PP
In order to evaluate the maximum annual temperature in the housing it is 
advisable to define a mathematical model of the heat transmission and 
solve it for the conditions imposed by the site climate, the soil nature, 
the power consumption,\ etc. 
.PP
The relevant calculation can be handled by computer making it possible 
to rapidly investigate the effect of the different parameters. 
.PP
In critical condition, that is in soil of poor characteristics,
advantage can be taken putting around the housing a backfilling material of
good thermal conductivity. The effect of such an action can be previously
verified by computer.
.RT
.sp 2P
.LP
3.2
	\fIGuidelines of the calculus\fR 
.sp 1P
.RT
.PP
The heat transmission from the atmosphere to the soil is described by the 
equation 
\v'6p'
.RT
.ad r
.ad b
.RT
.LP
where
.LP
	A
	Mean value of the atmospheric temperature
.LP
	B
	Amplitude of the thermal oscillation at the ground surface
.LP
	\(*g
	Coefficient of diffusion
.LP
	\fIy\fR 	Depth
.PP
The temperature is a function of the time and depth only and the resulting 
field has horizontal isothermal surfaces. 
.PP
The power dissipated in the housing determines a heat flux on the
walls of the container and a two\(hydimensional thermal field in the soil.
.bp
.PP
The relevant equation is the
\v'6p'
.RT
.ad r
.ad b
.RT
.LP
where
.LP
	\fIF\fR \ (\fIx\fR ,\fIy\fR ,\fIt\fR )
	takes into account the
presence
of thermal sources in the soil
.LP
	C
	Specific heat of the soil
.LP
	\(*z
	Density of the soil
.LP
	k
	Thermal conductivity of the soil.
.PP
The problem can be further simplified neglecting the
term\ 
@ { (*d\fIT\fR } over { (*d\fIt\fR } @ .
.PP
In fact the temperature in the soil is subjected to a slow variation and 
can be considered as steady in the short period. 
.PP
Solve the equation
\v'6p'
.RT
.ad r
.ad b
.RT
.LP
and introducing the \*Qinitial condition\*U of the (1) for the considered 
time, the temperature distribution in the soil can be plotted in a discrete 
number of 
points.
.PP
The centreline temperature in the housing is calculated from heat transfer 
relationships for natural convection on vertical walls: 
Nu\ =\ M.\ (G
r
 | (mu | r)\uN\d where NU\ =\ Nusselt number;
GR\ =\ Grashof number; Pr\ =\ Prandtl number; M, N are constants to be 
empirically determined. 
.PP
An example of calculated thermal field is given in Figure\ 4 where the 
isothermal lines substitute the local temperature values plotted by 
computer.
.RT
.LP
.rs
.sp 27P
.ad r
\fBFigure 4, (N), p.\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.sp 2P
.LP
3.3
	\fIConclusion\fR 
.sp 1P
.RT
.PP
The temperature in the underground housing depends on site climate, type 
of soil, depth, time of the year, equipment dissipation. 
.PP
A mathematical analysis of the heat transmission makes it possible to evaluate 
the maximum temperature in the housing taking into account the effect of 
the parameters involved. 
.PP
The use of selected backfilling material can be considered and the
resulting effect evaluated.
.RT
.ce 1000
HOUSING\ TYPE\ :\ CAI/24
.sp 1P
.RT
.ce 0
.sp 1P
.ce 1000
Temperature at steady state (\(de | )
.sp 9p
.RT
.ce 0
.sp 1P
.ce 1000
Housing dimensions (m) \(es 0.85 h 0.9
.ce 0
.sp 1P
.LP
	Dissipated power (watt)
	\ 100
.sp 9p
.RT
.LP
	Month
	\ \ \ 8
.LP
	Mean temperature of the site (\(de | )
	\ \ 12.7 
.LP
	Amplitude of the thermal variation (\(de | )
	\ \ 11.7
.LP
	Thermal\ conductivity\ of\ the
soil\ (W\ m\uD\dlF261\u1\d K\uD\dlF261\u1\d)
	\ \ \ 0.44
.LP
	Density of the soil (kg | (mu | \uD\dlF261\u3\d)
	1550
.LP
	Specific heat of the soil
(J\ kg\uD\dlF261\u1\d K\uD\dlF261\u1\d)
	1255
.LP
	Thermal conductivity of the backfilling
material (W\ m\uD\dlF261\u1\d\ K\uD\dlF261\u1\d)
	\ \ \ 0.8
.LP
	Depth of the backfilling material (m)
	\ \ \ 0.4
.LP
	External radius of the backfilling material (m)
	\ \ \ 1.2
.sp 2P
.LP
	\fBReference\fR 
.sp 1P
.RT
.LP
[1]
	 JEN\(hyHU\(hyCHANG: Ground Temperature, \fIBlue Hill Meteorological\fR 
\fIObservatory, Harward University\fR , 
Vol.\ I,\ II \(em Hilton\ 86,
Massachusetts,\ 1958.
.sp 2P
.LP
	\fBBibliography\fR 
.sp 1P
.RT
.LP
KREITH (F.): Principles of heat transfer, \fIInt. Textbook Co.\fR , Scr
	anton
Pa.
.LP
CARLSLAW JAEGER: Conduction of heat in solids, \fIOxford Press\fR .
.sp 2P
.LP
\fBSupplement\ No.\ 35\fR 
.RT
.sp 2P
.sp 1P
.ce 1000
\fBGUIDELINES\ CONCERNING\ THE\ MEASUREMENT\ OF\ WANDER\fR 
.EF '%	Fascicle\ III.5\ \(em\ Suppl.\ No.\ 35''
.OF '''Fascicle\ III.5\ \(em\ Suppl.\ No.\ 35	%'
.ce 0
.sp 1P
.ce 1000
(Contribution from United States of America, referred to in
.sp 9p
.RT
.ce 0
.sp 1P
.ce 1000
Recommendations G.812 and G.824)
.ce 0
.sp 1P
.LP
	\fBWander measurement methodology\fR 
.sp 1P
.RT
.PP
\fB
The purpose of this Supplement is to present one suitable method of verification 
of timing accuracy of clocks. Guidelines concerning the 
measurement of jitter are contained in Supplement No.\ 38 of the
O\(hySeries.
.RT
.sp 2P
.LP
\fB1\fR 	\fBOutput wander measurement\fR 
.sp 1P
.RT
.sp 1P
.LP
1.1
	\fISlave clock\fR 
.sp 9p
.RT
.PP
The measurement strategy is to be able to derive the values of the model 
parameters contained in the Annex to Recommendation\ G.812 for the slave 
clock under test. 
.PP
Once these parameter values have been obtained compliance with the
specifications contained in Recommendation\ G.812 may be verified.
.bp
.PP
To adequately characterize the performance of a slave clock a series of 
tests must be performed. In general, the test fall into the three categories 
of operation: 
.RT
.LP
	1)
	ideal operation;
.LP
	2)
	stressed operation;
.LP
	3)
	holdover operation.
.sp 1P
.LP
1.1.1
	\fITest configuration\fR 
.sp 9p
.RT
.PP
The objective of the test procedure is to be able to estimate the parameters 
in the clock model described above for a given clock under test. The architecture 
for a clock testing arrangement is shown in Figure\ 1. The 
components and their interconnection are described next.
.RT
.LP
.rs
.sp 25P
.ad r
\fBFigure 1, (N), p.\fR 
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
1.1.1.1
	\fIReference clock\fR 
.sp 9p
.RT
.PP
The test configuration is designed to provide the clock under test with 
a primary rate digital reference timed from a stable reference oscillator. 
In clock testing, it is the relative phase\(hytime compared to the reference 
input that is critical 
.FS
In holdover testing, the longer term stability and drift of the reference 
oscillator is important. 
.FE
. Thus, the absolute accuracy of the reference input is not critical. What 
is important is that short\(hyterm 
instability of the reference oscillator be small to ensure low measurement
noise and a low background tracking error in the control loop of the clock
being tested.
.bp
.RT
.sp 1P
.LP
1.1.1.2
	\fIDigital reference simulation\fR 
.sp 9p
.RT
.PP
The testing arrangement is designed to provide a primary rate
digital reference with impairment to the clock to allow for stress testing 
of the clock. To accomplish this a primary rate digital signal simulator 
and 
analyzer is employed that has the capability to be externally synchronized. 
For the 1544\ kHz primary rate digital signal 
.FS
The following discussion is
applicable in an analogous manner to the 2048\ kHz primary rate digital
signal.
.FE
a 1544\ kHz timing signal is supplied to the simulator/analyzer to control 
outgoing transmit timing. The 1544\ kHz signal is produced via a 
distribution amplifier and synthesizer line tap. This distribution arrangement 
allows one to develop multiple taps of timing signals synthesized from 
the 
10\ MHz input from the reference oscillator. Each line tap is a dedicated
synthesizer producing the timing signal required. The jitter produced from
these synthesizers should be less than 1000\ ps rms.
.PP
The primary rate impairment simulator is programmed via an IEEE\ 488
control bus to produce the desired interruption events to stress the clock. 
The primary rate digital signal is next bridged through a jitter generator 
and 
receiver. The jitter generator is used to insert background jitter to the
digital signal. It is important to simulate a realistic level of background
jitter for several reasons. Primarily, when interruptions occur the background 
jitter can be a major source of phase build\(hyout error as the synchronization 
unit attempts to bridge the interruption. Secondly, the jitter transfer
characteristics of the clock can be evaluated.
.PP
The jitter generation unit is provided an external jitter modulation input. 
The jitter signal used is bandlimited white noise. A signal from a white 
noise source is filtered using a low pass single pole filter with 150\ 
Hz 3\ dB cutoff. The main reason for lowpass filtering the jitter is to 
avoid producing bit errors from high frequency alignment jitter. The jitter 
power should be set to reflect realistic jitter levels in the network. 
It is important that 
sinusoidal jitter be avoided as a test jitter input, as certain phase detection 
techniques are very insensitive to sinusoidal jitter. 
.RT
.sp 1P
.LP
1.1.1.3
	\fIOutput timing signal recovery\fR 
.sp 9p
.RT
.PP
To test a clock, reference input is provided from the output of the jitter 
generator. To recover the output timing signal from the clock, an 
outgoing primary rate signal is selected from the unit controlled by the 
clock under test. This digital signal is connected to the receive portion 
of the 
Primary Rate Signal Simulator and Analyzer. In this unit the receiver timing
function is decoupled from the transmit timing used in the generator. The
receiver extracts a 4\ kHz frame timing signal from the input signal and
provides this timing signal at an external port. This 4\ kHz timing signal is
phase coherent with the outgoing timing from the clock under test.
.RT
.sp 1P
.LP
1.1.1.4
	\fIPhase\(hytime data collection\fR 
.sp 9p
.RT
.PP
A counter is used to observe the relative phase\(hytime error of the output 
4\ kHz timing signal compared to a reference 4\ kHz timing signal. The 
reference 4\ kHz timing signal is derived from the distribution amplifier and
synthesizer units. The synthesizer jitter in generating the 4\ kHz reference
signal is less than 1000\ ps. By performing the phase comparison at 4\ kHz the
observation range of phase variation is 250\ \(*ms. If care is given to start a
test near the centre of this range, there should not be a problem associated
with cycle slipping for all tests except holdover testing. However, even 
this range can be extended by resolving cycle slips in the data collection 
software.
.PP
In reality, the measurement resolution is limited by the intrinsic
jitter in the counter as well as trigger error. Experience has shown that 
the measurement resolution jitter can be maintained below 100\ ps rms with 
reasonable care given to cabling and trigger levels. More importantly, the
overall background jitter noise level can be checked prior to testing to
ensure proper performance. For the components used in the particular system
described, overall jitter levels of 1000\ ps rms are typically attainable. 
This is more than adequate for measuring the levels of phase stability 
expected from clocks. 
.bp
.RT
.sp 1P
.LP
1.1.1.5
	\fIData collection\fR 
.sp 9p
.RT
.PP
An instrument control computer should be used to automate the
testing procedure and collect and analyze the phase\(hytime data. The control
computer is interfaced via an IEEE\ 488 bus to both the Counter and the 
Primary Rate Digital Signal Simulator and Analyzer. 
.PP
A key function of the control computer is to gather phase\(hytime data
from the counter. The instrument controller obtains a phase\(hytime sample from
the counter every 10\ seconds. The counter is programmed to average 4000\ 
samples over a 3\ second window and return the average to the controller. 
The resulting measurement bandwidth is 0.33\ Hz. The phase\(hytime data 
is processed in real\(hytime to obtain running estimates of the Allan variance 
for\ 10, 100, 1000 and\ 10 | 00 second observation intervals. The program 
also calculates a running estimate of the frequency departure and the drift. 
.RT
.sp 1P
.LP
1.1.1.6
	\fIData analysis\fR 
.sp 9p
.RT
.PP
The objective of the data analysis is to estimate from the data the parameters 
associated with the clock model. From the Allan variance data, one can 
determine the presence of either the white noise PM or white noise FM 
components expected from the model. The frequency departure estimator is the
y\db\\di\\da\\ds\uterm in the model, and the drift estimator\ D is the drift
component in the model.
.RT
.sp 1P
.LP
1.1.2
	\fIBasic technique and procedure\fR 
.sp 9p
.RT
.PP
This paragraph contains the basic techniques and procedures for
testing the three categories of slave clock operation. Appendix\ I provides
examples of the application of these test using actual measurement
data.
.RT
.sp 1P
.LP
1.1.2.1
	\fIIdeal operation\fR 
.sp 9p
.RT
.PP
The purpose of this testing is to obtain a baseline performance
metric for a clock. The model predicts that clocks under ideal conditions
should produce a white noise PM phase instability. This white noise PM 
should be small as it represents the best case performance of a clock (clearly 
less 
than 1\ \(*ms based on current MRTIE output requirements). It should be 
measured in the presence of realistic levels of jitter to assure acceptable 
jitter 
transfer.
.PP
In the standard test procedure described, the bandwidth of the
measurement is 0.33\ Hz. In some clock designs, there is significant noise
between this 0.33\ Hz cutoff and the 10\ Hz cutoff associated with jitter. 
It is important to evaluate the jitter in this band. This could be accomplished 
by 
developing an additional measurement program to capture this fast wander
data.
.RT
.sp 1P
.LP
1.1.2.2
	\fIStressed operation\fR 
.sp 9p
.RT
.PP
This area of testing is critically important to adequately evaluate clocks. 
The difficulty in this testing is selection of the appropriate 
disruption events. For some clocks any event that appears as a severely 
errored second will produce a phase build\(hyout event. In some clocks 
any outage or 
spurious noise spikes will perturb a counter in the phase detection producing 
a spurious phase hit which may or may not be phase built\(hyout depending 
on its 
severity. On the other hand, clocks can be designed to observe the framing
pulse position to extract phase. In such clocks, an interruption need not
produce a phase build\(hyout event unless there is an actual shift in the 
framing pulse position (for example a protection switch event). 
.PP
It is proposed that one stress test which should be performed is to
simulate an SES event with a short outage (100\ ms) at a rate of 10\ SES 
per day in the presence of background input jitter. Typically an outage 
of this 
magnitude will force a clock to attempt to phase build\(hyout without switching
references. An example of this stress test is given in the next section and
should serve to clarify the concepts and the significance of the results.
.PP
Other stress inputs should also be considered in evaluating a
clock.
.RT
.LP
	\(em
	\fIError bursts\fR  |  An error burst can be simulated in
which the underlying timing waveform is not perturbed. Under
this condition, it would be advantageous for a clock not to
phase build\(hyout. Such a test would gain in importance if it is
determined that the majority of error burst events are actually
pure data errors with no perturbation in timing.
.bp
.LP
	\(em
	\fIPhase bit\fR  |  Phase hits are produced by protection
activity, as well as from other clocks. Phase hits are
interruption events that should either force a phase build\(hyout
event or inadvertently be followed by the clock. In either case
they will degrade a clock's performance. This is an area for
further study.
.LP
	\(em
	\fIRestart events\fR  |  Restart events are a phenomena
associated with certain clocks. A restart event is associated
with a clock giving up its current state, and defaulting back
to its initial conditions. The results are a transient event
which can be significant. Restart events should not happen
during normal clock operation, and thus should not likely be
included in a general clock testing plan. However, it is
important that the behaviour be better understood and
controlled.
.LP
	\(em
	\fIFrequently hit\fR  |  It is important that clocks do not
follow references that exhibit large frequency hits. However the
ability to detect frequency hits is closely tied to the
selection of the tracking bandwidth of a given clock PLL. The
solution to the problem will depend on the degree to which the
bandwidth of various clocks in a network can be
standardized.
.sp 1P
.LP
1.1.2.3
	\fIHoldover operation\fR 
.sp 9p
.RT
.PP
In holdover testing, the objective is to estimate the initial
frequency offset (y\db\\di\\da\\ds\u) and the Drift (D) of the clock model. 
The initial frequency offset is dependent on the accuracy of the frequency 
estimate obtained in the control loop, and the frequency settability of 
the local 
oscillator. It is important to test holdover from a reasonable stress condition 
prior to holdover to capture the control loops capability of obtaining 
an 
accurate frequency estimate.
.PP
In determining the drift estimate, one critical factor for quartz
oscillators is that it typically takes observation intervals lasting over 
days to obtain a statistically significant drift estimator. This is a hard 
reality that cannot be avoided. In addition, attention must be placed on 
the 
temperature conditions maintained during the test. This is a subject for
further study.
.RT
.sp 2P
.LP
1.2
	\fIPrimary reference clock\fR 
.sp 1P
.RT
.PP
This section requires further study.
.RT
.ce 1000
APPENDIX\ I
.ce 0
.ce 1000
(to Supplement No. 35)
.sp 9p
.RT
.ce 0
.ce 1000
\fBExample applications\fR 
.sp 1P
.RT
.ce 0
.PP
This section presents the results of the application of some of
the testing procedures for two clocks. It is important to point out that the
two clocks tested have different internal architectures. The main result 
of the tests is that the model for clock performance was supported. This 
model can be summarized as follows: 
.sp 1P
.RT
.LP
	1)
	For short observation intervals outside the tracking
bandwidth of the PLL, the stability of the output timing signal
is determined by the short\(hyterm stability of the local
synchronizer time base.
.LP
	2)
	In the absence of reference disruptions, the stability of
the output timing signal behaves as a white noise PM process as
the observation period is increased to be within the tracking
bandwidth of the PLL.
.LP
	3)
	In the presence of disruptions, the stability of the output
timing signal behaves as a white noise FM process as the
observation period is increased to be within the tracking
bandwidth of the PLL.
.LP
	4)
	In the presence of disruptions, the output timing signal
may incur a systematic frequency offset with respect to the
reference. This results from a bias in the phase build\(hyout when
reference is restored.
.PP
The specific test results are described below.
.bp
.sp 2P
.LP
I.1
	\fILocal clock evaluation\fR 
.sp 1P
.RT
.PP
The results described in this section are for actual performance
data.
.RT
.sp 1P
.LP
I.1.1
	\fIUnstressed primary rate input tests\fR 
.sp 9p
.RT
.PP
The first test performed was to evaluate the timing signal output under 
ideal reference input conditions. The primary rate reference input is 
produced by the generator timed from the Caesium reference. The jitter 
outside the tracking bandwidth of the stratum 3\ PLL is much less than 
1\ ns. Typically, 300\ ps as measured by the counter. 
.PP
For this test, the jitter test set was bypassed, and the primary rate from 
the primary rate simulator and analyzer was fed directly into the 
synchronizer. The test was run for 67\ hours. The results are presented in
Figure\ I\(hy1. The square root of the Allan variance is plotted vs. observation 
time. The data points marked by triangles apply to this test.
.PP
The test results are consistent with the model. For observation times outside 
the tracking bandwidth of this PLL (less than 60\ seconds), the Allan 
variance indicated a white FM noise resulting from the local quartz oscillator. 
As the observation time increases, the PLL tracks the reference and the 
noise process converges to white FM. 
.PP
The magnitude of the white PM noise is 85\ ns rms. One component of
this noise is the rms time error of the oscillator in 60\ seconds (the 
bandwidth of this PLL is 1/60\ sec). In addition, there is a component 
resulting from the resolution of the phase detector. A phenomena that arises 
in digital loops is that the phase error can make excursions of at least 
one bit in either 
direction of the nominal setpoint. This effect is reduced when the input has
jitter on the order of a phase detector bit.
.RT
.sp 1P
.LP
I.1.2
	\fIStressed primary rate input test\fR 
.sp 9p
.RT
.PP
The purpose of this test is to emulate the behaviour of the
synchronizer under stress conditions that arise in actual networks. For this
test, a short outage event was produced under program control by the primary
rate simulator and analyzer every 15\ minutes. The outage events duration was
randomized with a uniform distribution over the range of 10\ to 100\ ms.
.PP
For this test, the jitter set was bypassed, and the primary rate
signal from the primary rate simulator and analyzer was fed directly into 
the synchronizer. The test was run for 50\ hours. The results are presented 
in 
Figure\ I\(hy1. The square root of the Allan variance is plotted vs. observation 
time. The data points marked by plus signs apply to this test.
.RT
.sp 1P
.LP
I.1.2.1
	\fIAllan variance results\fR 
.sp 9p
.RT
.PP
The test results are consistent with the model. For observation
times outside the tracking bandwidth of this PLL (less than 60\ seconds), the
Allan variance indicates a white FM noise resulting from the local quartz
oscillator. As the observation time increases, the PLL is experiencing a
disruption every 900\ seconds. The residual phase build\(hyout error accumulates 
and produces a random walk in phase (white noise FM). The build\(hyout 
error per disruption is calculated as 180\ ns\ rms. 
.RT
.sp 1P
.LP
I.1.2.2
	\fISystematic frequency offset\fR 
.sp 9p
.RT
.PP
The stress test data shows a statistically significant frequency
offset. The frequency offset over the 50\ hour test was 3\ \(mu\ 10\uD\dlF261\u1\d\u1\d. 
Given the white FM noise, the rms error is 1.5\ \(mu\ 10\uD\dlF261\u1\d\u1\d. 
These numbers reflect a bias error in the phase build\(hyout in the range 
of 15\ to 45\ ns. Such bias errors in clocks result in frequency offsets. 
The implications of this is that to some extent all clocks in a network 
operate plesiochronously. Given a worse case level of disruption of ten 
per day the resulting frequency offset is of the order of parts in\ 10\u1\d\u2\d. 
.bp
.RT
.LP
.rs
.sp 35P
.ad r
\fBFigure I\(hy1, (N), p.17\fR 
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
I.1.2.3
	\fISignificance of stress test results\fR 
.sp 9p
.RT
.PP
To obtain a meaningful interpretation of the stress test results
one must consider the disruption level. In this test the disruption level 
was 100\ disruptions per day. This is an order of magnitude greater than 
what can be expected on actual primary rate links. In this particular PLL 
the build\(hyout 
error process is independent from one event to the next. This can be proven 
by testing at several disruption levels. The results indicated a rms error 
of 
180\ ns per disruptions. Given 10\ disruptions per day the resulting daily rms
error is 570\ ns.
.RT
.sp 2P
.LP
I.2
	\fITransit clock evaluation\fR 
.sp 1P
.RT
.PP
The results described in this section are for actual performance
data.
.RT
.sp 1P
.LP
I.2.1
	\fIUnstressed primary rate input test\fR 
.sp 9p
.RT
.PP
The first test performed was to evaluate the timing signal output under 
ideal reference input conditions. The primary rate reference input is 
produced by the primary rate simulator and analyzer timed from the Caesium
reference. The jitter outside the tracking bandwidth of the stratum\ 3 PLL is
much less than 1\ ns. Typically, 300\ ps as measured by the counter.
.bp
.PP
For this test, the jitter test set was included. The jitter test set was 
given an external jitter modulation input. The jitter signal was band 
limited white noise. A single pole filter was employed with a 150\ Hz 3\ dB
cutoff. The jitter was low passed filter to avoid producing framing errors
resulting from high frequency alignment jitter. The external signal was
adjusted to achieve a peak\(hyto\(hypeak jitter level of 1.5\ \(*ms. The 
test was run for 23\ hours. The results are presented in Figure\ I\(hy2. 
The square root of the Allan variance is plotted vs. observation time. 
The data points marked by triangles apply to this test. 
.PP
The test results are consistent with the model. For observation times outside 
the tracking bandwidth of this PLL (less than 450\ seconds), the Allan 
variance indicated a white FM noise resulting from the local quartz oscillator. 
As the observation time increases, the PLL tracks the reference and the 
noise process converges to white PM. 
.PP
The magnitude of the white PM noise is 6\ ns rms. This is an
exceptionally good number and results from the tight time constant for 
the loop (450\ seconds). In this case the input jitter prevents the edge 
jumping 
effects.
.RT
.LP
.rs
.sp 35P
.ad r
\fBFigure I\(hy2, (N), p.\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.sp 1P
.LP
I.2.2
	\fIStressed primary rate input test\fR 
.sp 9p
.RT
.PP
The purpose of this test is to emulate the behaviour of the
synchronizer under stress conditions that arise in actual networks. For this
test, a short outage event was produced under program control by the primary
rate simulator and analyzer every 30\ minutes. The outage events duration was
randomized with a uniform distribution over the range of 10\ to 100\ ms.
.PP
For this test, the jitter test set was included. The jitter test set was 
given an external jitter modulation input. The jitter signal was 
bandlimited white noise. A single pole filter was employed with a 150\ 
Hz 3\ dB cutoff. The jitter was low passed filter to avoid producing framing 
errors 
resulting from high frequency alignment jitter. The external signal was
adjusted to achieve a peak\(hyto\(hypeak jitter level of 1.5\ \(*ms. The 
test was run for 70\ hours. The results are presented in Figure\ I\(hy2. 
The square root of the Allan variance is plotted vs. observation time. 
The data points marked by plus signs apply to this test. 
.RT
.sp 1P
.LP
I.2.2.1
	\fIAllan variance results\fR 
.sp 9p
.RT
.PP
The test results are consistent with the model. For observation
times outside the tracking bandwidth of this PLL (less than 450\ seconds), 
the Allan variance indicated a white FM noise resulting from the local 
quartz 
oscillator. As the observation time increases, the PLL is experiencing a
disruption every 1800\ seconds. The residual phase build\(hyout error accumulates 
and produces a random walk in phase (white noise FM). The build\(hyout 
error per disruption is calculated at 34\ ns rms. A contributor to this 
error is the input primary rate jitter. The algorithm averages the input 
to improve the estimate of the phase error to build\(hyout. 
.RT
.sp 1P
.LP
I.2.2.2
	\fISystematic frequency offset\fR 
.sp 9p
.RT
.PP
The stress test data shows a statistically insignificant frequency offset. 
The frequency offset over the 70\ hour test was 6\ \(mu\ 10\uD\dlF261\u1\d\u3\d. 
Given the white FM noise, the rms error is 1.5\ \(mu\ 10\uD\dlF261\u1\d\u2\d. 
Given this 
uncertainty, there is no indication of a bias in the data. In the worse case
the bias should not be more than the uncertainty level of
1.5\ \(mu\ 10\uD\dlF261\u1\d\u2\d.
.RT
.sp 1P
.LP
I.2.2.3
	\fISignificance of stress test results\fR 
.sp 9p
.RT
.PP
To obtain a meaningful interpretation of the stress test results
one must consider the disruption level. In this test the disruption level 
was 48\ disruptions per day. This is five times greater than what can be 
expected on actual primary rate links. In this particular PLL the build\(hyout 
error process should be independent from one event to the next based on 
a knowledge of the 
PLL design. This can be proven by testing at several disruption levels. The
results indicated an rms error of 34\ ns per disruption. Given 10\ disruptions
per day, the resulting daily rms error is 100\ ns.
.RT
.sp 2P
.LP
I.3
	\fIAllan variance confidence limits\fR 
.sp 1P
.RT
.PP
Sample variances (like sample Allan variances) are distributed as chi\(hysquare. 
Based on J.\ Barnes work described in\ [1], the confidence interval for 
the Allan variance can be determined assuming a given noise process. In 
calculating the sample Allan variances a complete overlap of lag intervals 
was used. This is the most efficient use of data. However, it is incorrect 
to 
assume independence in overlapping samples when calculating confidence
intervals. This is described in complete detail in\ [1]. For brevity, the
methods for calculating the confidence interval described in reference\ 
[1] were employed. 
.PP
The 90% confidence factors for white PM noise are bounded within 0.9 and\ 
1.1 for all lag times up to\ 10,000 assuming an observation period of a 
day. For white FM noise over a day observation interval the confidence 
factors were as follows. For 1000\ second lag interval the lower bound 
is\ 0.9, and the upper bound is\ 1.2. At\ 10 | 00 the confidence factors 
are\ 0.75 and\ 1.5. 
.bp
.PP
As an example of what these factors mean consider the white FM noise component 
in Figure\ I\(hy2 (plus sign tagged data). For the 10 | 00\ second lag, 
the square root of the sample variance is\ 8\ \(mu\ 10\uD\dlF261\u1\d\u2\d. 
The 90% confidence 
interval for the true variance is bounded by the confidence factors multiplied 
by the sample variance. This leads to the square root of the Allan variance 
being bounded between\ 6.9\ \(mu\ 10\uD\dlF261\u1\d\u2\d and\ 9.8\ \(mu\ 
10\uD\dlF261\u1\d\u2\d with a 90% confidence level. 
.RT
.sp 2P
.LP
	\fBReference\fR 
.sp 1P
.RT
.LP
[1]
	BARNES (J. | .): Data Analysis and Confidence Intervals,
\fINBS Time and Frequency Seminar Notes\fR , chapter\ 6, August,\ 1986.
.sp 2P
.LP
\fBSupplement\ No.\ 36\fR 
.RT
.sp 2P
.sp 1P
.ce 1000
\fBJITTER\ AND\ WANDER\ ACCUMULATION\ IN\ DIGITAL\ NETWORKS\fR 
.EF '%	Fascicle\ III.5\ \(em\ Suppl.\ No.\ 36''
.OF '''Fascicle\ III.5\ \(em\ Suppl.\ No.\ 36	%'
.ce 0
.sp 1P
.ce 1000
(Referred to in Recommendation G.824)
.sp 9p
.RT
.ce 0
.sp 1P
.PP
The present Supplement describes a model which has been used to
compute jitter/wander accumulation in digital networks arising from cascaded
digital regenerators and asynchronous digital multiplexes. This model does 
not include other sources of wander generation; e.g., environmental, disruptions 
in synchronization reference distribution,\ etc. 
.sp 1P
.RT
.sp 2P
.LP
\fB1\fR \fBJitter and wander accumulation \(em Digital regenerator component\fR 
.sp 1P
.RT
.PP
The most widely used model of regenerator jitter/wander
accumulation, attributed to Chapman\ [1], treats the regenerator as linear,
shift\(hyinvariant system. In order to compute the accumulated jitter/wander
after N cascaded regenerators, intrinsic regenerator jitter/wander is
categorized in terms of \*Qrandom\*U and \*Qsystematic\*U components. Chamzas 
model of regenerator jitter/wander accumulation\ [2] addresses how stochastic 
variations in regenerator retiming circuits affect jitter/wander accumulation. 
The results of this study demonstrate that use of the appropriate \fImean\fR 
jitter/wander 
transfer characteristic in the identical regenerator accumulation model,
summarized above, provides a very good estimate to jitter/wander accumulation 
computed assuming a stochastic variation of retiming circuits. 
.PP
Using Chapman's model for a chain of N \fIidentical\fR  | regenerators,
defining \fIH\fR\d1\u(\fIj\fR \(*w) as the jitter/wander transfer characteristic 
for one regenerator, and redefining the random and systematic components 
as 
completely uncorrelated and correlated components, respectively,
.RT
.LP
	\(em
	the power spectral density of the random jitter/wander
component is:
\v'6p'
.ad r
.ad b
.RT
.LP
	where ?71
$$Ei:\fIR\fR :\fIi\fR 1_ | is the constant, internally
generated, random (pattern independent plus uncorrelated pattern
dependent) jitter/wander power spectral density for one
regenerator.
.LP
	\(em
	the power spectral density of the systematic jitter/wander
component is:
\v'6p'
.ad r
.ad b
.RT
.LP
	where ?71
$$Ei:\fIS\fR :\fIi\fR 1_  | s the constant, internally
generated, systematic (correlated pattern dependent)
jitter/wander power spectral density for one regenerator.
?71
$$Ei:\fIR\fR :\fIi\fR 1_ and ?71
$$Ei:\fIS\fR :\fIi\fR 1_ can be estimated from
practical measurements based upon the regenerator's
jitter/wander response to short and long word lengths from a
pattern generator, and correlation studies.
.PP
When there is no peaking in the regenerator jitter/wander transfer characteristic, 
the systematic jitter/wander accumulates much more rapidly than the random 
jitter/wander\ [1],\ [4],\ [5]; as a result, random jitter/wander 
accumulation is often ignored. However, for a large number of regenerators 
with peaking in the jitter/wander transfer characteristic, the total jitter/wander 
accumulation can be dominated by the random component. 
.bp
.sp 2P
.LP
\fB2\fR 	\fBJitter and wander accumulation \(em Asynchronous digital multiplex
component\fR 
.sp 1P
.RT
.PP
With Gaussian input jitter/wander, having an rms amplitude of\ \(*s,
and double\(hysided power spectral density \(*h\fI\fI\d\fIi\fR\\d\fIn\fR\u\ (
\fIf\fR ),
the unfiltered multiplex intrinsic jitter/wander is given
by\ [6].
\v'6p'
.RT
.ad r
.ad b
.RT
.LP
	p
	Multiplexer stuffing ratio
.LP
	f
	jitter/wander frequency normalized by the multiplexer
maximum suffising frequency
.sp 2P
.LP
\fB3\fR 	\fBMethod of combination\fR 
.sp 1P
.RT
.PP
Assuming that the jitter/wander accumulation from each component
part can be modeled by filtered Gaussian randam variables, the power spectrum 
and rms amplitude after each component part 
.FS
The following equations are
valid for both single\(hy and double\(hysided power spectra and corresponding
transfer characteristics.
.FE
is computed as the accumulation due to the
preceding parts according to the following rules\ [3]:
.RT
.LP
	i)
	The jitter/wander spectrum at the output of a chain of
regenerators is the power sum of the jitter/wander generated by
the regenerators (equations\ [1] and\ [2]) and any jitter/wander
at the input of the chain, appropriately filtered by the
equivalent jitter/wander transfer characteristic. Thus, for
input jitter/wander, \(*h\fI\fI\d\fIi\fR\\d\fIn\fR\u\ (\(*w), the output
jitter/wander, \(*h\fI\fI\d\fIo\fR\\d\fIu\fR\\d\fIt\fR\u\ (\(*w), is given by
\v'6p'
.ad r
.ad b
.RT
.LP
	ii)
	The jitter/wander spectrum at the output of a demultiplexer
is the power sum of the unfiltered intrinsic multiplex
jitter/wander and the accumulated higher rate input
jitter/wander, attenuated by the desynchronizer jitter/wander
transfer characteristic. Thus, if \(*h\fI\fI\d\fIi\fR\\d\fIn\fR\\d,\\d1\u\ 
(\(*w) 
is the unfiltered intrinsic multiplex jitter/wander
and \(*h\fI\fI\d\fIi\fR\\d\fIn\fR\\d,\\d2\u\ (\(*w) is the accumulated 
higher rate 
input jitter/wander, the output jitter/wander,
\(*h\fI\fI\d\fIo\fR\\d\fIu\fR\\d\fIt\fR\u\ (\(*w) is given by
\v'6p'
.ad r
.ad b
.RT
.LP
	where \fIr\fR  | is the ratio of the multiplexer output frequency to tributary
frequency, and \fIG\fR (\fIj\fR \(*w) represents the desynchronizer
jitter/wander transfer characteristic.
.bp
.sp 2P
.LP
\fB4\fR 	\fBDefinition of peak\(hyto\(hypeak jitter/wander amplitude\fR 
.sp 1P
.RT
.PP
The probability that the jitter/wander exceeds a particular
threshold amplitude | | fIx\fR  |  \fIn\fR \ times in the time interval
(\fIt\fR , \fIt\fR \ +\ ?63\fIt\fR ) may be described by a Poisson density
function\ [3].
\v'6p'
.RT
.ad r
.ad b
.RT
.LP
where
\fIN\fR  | \fIx\fR )
is the average number of times/second that the threshold | | fIx\fR  |  
is exceeded. 
.PP
For Gaussian jitter/wander, with double\(hysided power spectral
density \(*h(\(*w), 
\fIN\fR  | \fIx\fR )
is given by\ [7]
\v'6p'
.ad r
.ad b
.RT
.PP
The probability that the jitter/wander doesn't exceed the
threshold during the time interval\ (\fIt\fR , \fIt\fR \ +\ ?63\fIt\fR ) is
\v'6p'
.ad r
.ad b
.RT
.LP
Solving for the threshold,
\v'6p'
.ad r
.ad b
.RT
.PP
If we assume that each time the threshold is crossed, an
undesirable event (impairment) may result, the mean time between impairments, 
MTBI, may be taken as 
\v'6p'
.ad r
.ad b
.RT
.LP
Thus, equation (9) may be expressed as
\v'6p'
.ad r
.ad b
.RT
.sp 2P
.LP
	\fBReferences\fR 
.sp 1P
.RT
.LP
[1]
	BYRNE (C. | .), KARAFIN (B. | .) and ROBINSON (D. | .) Jr.: Systematic
Jitter in a Chain of Digital Regenerators , \fIBell System Technical Journal\fR 
, 
November,\ 1983.
.LP
[2]
	CHAMZAS (C.) Accumulation of Jitter: A Stochastic Model, \fIAT&T\fR 
\fITechnical Journal\fR , Vol.\ 64, No.\ 1, January,\ 1985.
.LP
[3]
	 BATES (R. | . | .): A model for Jitter Accumulation in Digital Networks, 
\fIGlobecom' 83\fR , pp.\ 145\(hy149,\ 1983. 
.LP
[4]
	TRISCHITTA (P. | .): Jitter\(hyAccumulation in Fiber Optic Systems,
\fIRutgers\fR , The State University of New Jersey, May,\ 1986.
.LP
[5]
	 VARMA (E. | .) and WU (J.): \*QAnalysis of Jitter Accumulation in a Chain 
of PLL Timing Recovery Circuits\*U, \fIProceedings of the IEEE Globecom\fR 
, Vol.\ II, pp.\ 653\(hy657,\ 1982. 
.LP
[6]
	DUTTWEILER (D. | .): Waiting Time Jitter, \fIBell System Technical\fR 
\fIJournal\fR , Vol.\ 51, No.\ 1, pp.\ 165\(hy208,\ 1972.
.LP
[7]
	BENDAT (J. | .): Principles and Applications of Random Noise Theory,
\fIRobert E. Krieger Publishing Company\fR , Hungtington, New York,\ 1977.
.LP
.bp