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\v | 5i'
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\s12FASCICLE\ III.5
\v'4P'
.RT
.ce 0
.sp 1P
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\fBRecommendations\ G.801\ to\ G.961\fR \v'2P'
.ce 0
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\fBDIGITAL\ NETWORKS,\ DIGITAL\ SECTIONS\fR 
.EF '%	 \ \ \ ^''
.OF ''' \ \ \ ^	%'
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\fBAND\ DIGITAL\ LINE\ SYSTEMS\fR 
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\fBMONTAGE:\ \fR PAGE 2 = PAGE BLANCHE
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SECTION\ 8
.ce 0
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\fBDIGITAL\ NETWORKS\fR 
.ce 0
.sp 1P
.IP
\fB8.0\ \fR \fBGeneral aspects of digital networks\fR 
.sp 1P
.RT
.sp 2P
.LP
\fBRecommendation\ G.801\fR 
.RT
.sp 2P
.sp 1P
.ce 1000
\fBDIGITAL\ TRANSMISSION\ MODELS\fR 
.EF '%	Fascicle\ III.5\ \(em\ Rec.\ G.801''
.OF '''Fascicle\ III.5\ \(em\ Rec.\ G.801	%'
.ce 0
.sp 1P
.ce 1000
\fI(Malaga\(hyTorremolinos, 1984)\fR 
.sp 9p
.RT
.ce 0
.sp 1P
.sp 2P
.LP
	The\ CCITT
.sp 1P
.RT
.sp 1P
.LP
\fIconsidering\fR 
.sp 9p
.RT
.PP
(a)
that digital networks support a wide variety of connections for which digital 
transmission impairments and other performance parameters 
need to be controlled;
.PP
(b)
that, if proper control is not exercised, then under
certain circumstances, digital transmission impairments cause unacceptable
service degradations;
.PP
(c)
that various network performance objectives need to be
allocated to the elements of a digital network;
.PP
(d)
that equipment design objectives need to be formulated for individual digital 
elements; 
.PP
(e)
that networks need to be configured to a level of
transmission quality consistent with the needs of different services (voice 
and non\(hyvoice) and in particular of services in the ISDN; 
.PP
(f
)
that Administrations need to examine the effect on
transmission quality of possible changes of impairment allocation in national 
networks; 
.PP
(g)
that there is a need to test national rules for prima facie compliance 
with any impairment criteria which may be recommended by the CCITT for 
national and international systems; 
.PP
(h)
that guidelines need to be formulated governing the use of certain digital 
elements (e.g.\ satellite links, transcoders, digital pads, 
circuit multiplication devices, etc.),
.sp 1P
.LP
\fIrecommends\fR 
.sp 9p
.RT
.PP
that in the study of digital transmission impairments and other
performance parameters, the following network models and associated guidelines 
should be applied. 
.sp 2P
.LP
\fB1\fR 	\fBIntroduction\fR 
.sp 1P
.RT
.PP
Digital transmission network models are hypothetical entities of a defined 
length and composition for use in the study of digital transmission 
impairments (e.g.\ bit errors, jitter and wander, transmission delay,
availability, slip,\ etc.). The diversity of possible network situations
requires that individual models can only represent a small portion of typical 
real entities. However, a limited number of such models (e.g.\ 2 or\ 3) 
together may be sufficiently representative to provide a useful tool upon 
which studies may be based. 
.bp
.PP
The network models, where applicable, take account of the following
features:
.RT
.LP
	a)
	 physically reflect the length of the overall connection with some indication 
of frequency of occurrence, 
.LP
	b)
	identify boundaries between switching and transmission
elements,
.LP
	c)
	 give no indication of the means of implementing transmission between 
switching elements (e.g.\ metallic, optical, radio media, satellite 
etc.),
.LP
	d)
	describe in detail the user/network access arrangement in
the local portion (i.e.\ customer to local exchange),
.LP
	e)
	take account of all possible usages or be independent of
them,
.LP
	f
)
	reflect the use of additional digital processing
elements required in particular network configurations (e.g.\ A\(hy\(*m 
converters, 
digital pads, transcoders,\ etc.).
.PP
This Recommendation makes no statement in respect of the
electrical and physical environment in which the network models operate. 
These aspects are currently the subject of study. In the application of 
these network models to the study of specific digital impairment (e.g.\ 
errors) arbitrary 
judgements may need to be made concerning the significance, in particular, 
of the electrical environment. 
.sp 2P
.LP
\fB2\fR 	\fBHypothetical reference connection\fR \fB(HRX)\fR 
.sp 1P
.RT
.PP
A digital HRX is a model in which studies relating to overall
performance may be conducted, thereby facilitating the formulation of standards 
and objectives. In order to initiate studies directed at the performance 
of an ISDN, an all digital 64\ kbit/s connection is considered. Since the 
overall 
network performance objectives for any performance parameter need to be
consistent with user requirements, such objectives, in the main, should 
relate to a network model which is representative of the very long connection. 
The 
HRX shown in Figure\ 1/G.801 serves this purpose. It does not represent 
the rare worst case connection; although it does aim to encompass the vast 
majority of connections for each relation. Moreover, the difficulty of 
identifying every 
conceivable practical implementation of a connection and the undesirability 
of producing too many options naturally requires that this \*Qstandard 
HRX\*U may need to be appropriately modified in composition to suit the 
particular task in 
.PP
hand. A situation can be envisaged where many similar HRXs exist to serve
specific functions, but in all cases they are derivatives of the \*Qstandard
HRX\*U. The potential proliferation of HRXs prevent their inclusion in this
Recommendation. Any departure from the \*Qstandard HRX\*U may need to be 
shown in the Recommendation appropriate to that impairment or performance 
parameter. For example, see Recommendation\ G.821. They are not intended 
to be used for the 
design of transmission systems.
.RT
.PP
The diversity in composition is particularly apparent when a
distinction is made between average size and large countries and, therefore 
no one HRX can possibly accommodate such variations. In the process of 
apportionment the demarcation between national and international portions is
unimportant as in most instances the intrinsic quality of circuit comprising
both portions is the same. In contrast, however, the overall length is 
regarded as being critical and its choice is \*Qcountry size\*U independent. 
Accordingly, 
the level of impairment actually experienced over a real connection is
considered satisfactory if compatible with that stipulated for the longest 
HRX, taking due account of differences between the construction of the 
hypothetical and real connections. For a large proportion of real connections 
configured 
using equipment designs recommended by CCITT, the actual performance is 
likely to be significantly better. Those CCITT compliant connections which 
exceed the longest HRX in either length or complexity may not have controlled 
levels of 
performance; however, their impairment levels are unlikely to exceed those 
of the longest HRX by more than a factor of\ 2 and the design margins provided 
with individual items of equipment may well bring the impairment to within 
CCITT 
end\(hyto\(hyend performance specifications.
.PP
In formulating the above HRX no account was taken of the following
aspects:
.RT
.LP
	\(em
	maritime applications,
.LP
	\(em
	semi\(hyautomatic connections (i.e.\ auto\(hymanual),
.LP
	\(em
	standby routing in case of failure.
.PP
Two other HRXs have been included to facilitate studies over
shorter connections with a view to establishing the typical performance 
levels likely to be achieved over frequently realized international circuits. 
These 
are given in Figures\ 2/G.801 and 3/G.801.
.bp
.LP
.rs
.sp 47P
.ad r
\fBFigure 1/G.801, p. (\*`a l'italienne)\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.bp
.LP
.rs
.sp 13P
.ad r
\fBFigure 2/G.801, p.\fR 
.ad b
.RT
.LP
.rs
.sp 13P
.ad r
\fBFIGURE 3/G.801, p.\fR 
.ad b
.RT
.sp 2P
.LP
\fB3\fR 	\fBHypothetical reference digital link (HRDL)\fR 
.sp 1P
.RT
.PP
To facilitate the study of digital transmission impairments
(e.g.\ bit errors, jitter and wander, slip, transmission delay) it is necessary 
to define network models comprising a combination of different types of 
transmission elements (e.g.\ transmission systems, multiplexers, demultiplexers, 
digital pads, transcoders). Such a model is defined as a 
Hypothetical
Reference Digital Link
(HRDL). The exact length and composition in respect of the number, type 
and disposition of equipments will depend on the digital 
impairment under study. For example, in the analysis of jitter accumulation 
in a network both transmission systems and muldexes would need to be included 
to take account of the different jitter characteristics exhibited by such 
equipment types. In addition the HRDL can be regarded as a constituent 
element of an HRX thus permitting the apportionment of overall performance 
objectives to a shorter model. A length of 2500\ km is considered as a 
suitable distance 
for a HRDL.
.PP
The formulation of such models is the subject of further study.
.PP
In CCIR Recommendations the term Hypothetical Reference Digital Path (HRDP) 
is sometimes used. This is equivalent to a Hypothetical Reference 
Digital Link (see Definition\ 3005 in Recommendation\ G.701).
.RT
.sp 2P
.LP
\fB4\fR 	\fBHypothetical reference digital section (HRDS)\fR 
.sp 1P
.RT
.PP
To accommodate the performance specification of transmission
systems (i.e.\ digital line and radio systems) it is necessary to introduce a
Hypothetical Reference Digital Section
(HRDS). Such a model is defined in Figure\ 4/G.801 for each level in the 
digital hierarchies defined in 
Recommendation\ G.702. The input and output ports are the recommended interfaces 
as given in Recommendation\ G.703 for hierarchical bit rates. The lengths 
have been chosen to be representative of digital sections likely to be 
encountered in real operational networks, and are sufficiently long to 
permit a realistic performance specification for digital radio systems. 
The model is homogeneous in that it does not include other digital equipments 
such as 
multiplexers/demultiplexers. This entity can form a constituent element of a
HRDL.
.bp
.RT
.LP
.rs
.sp 13P
.ad r
\fBFigure 4/G.801, p.\fR 
.sp 1P
.RT
.ad b
.RT
.PP
It is possible to relate the two following types of performance
requirement to an HRDS:
.LP
	\(em
	the Network Performance Objectives (NPO) which are the
objectives to be realized in a real network;
.LP
	\(em
	 the Equipment Design Objectives (EDO) which provide guidance to the designer 
of systems using specific transmission media and transmission techniques. 
.PP
\fINote\ 1\fR \ \(em\ The Equipment Design Objectives which normally appear 
in the appropriate transmission and switching system recommendations are 
formulated to ensure compatibility with the corresponding network performance 
objectives. 
.PP
\fINote\ 2\fR \ \(em\ An explanation of a Network Performance Objective and an
Equipment Design Objective is given in Recommendation\ G.102.
.PP
\fINote\ 3\fR \ \(em\ The formulation of a homogeneous entity of a realistic
length permits specification and commissioning acceptance testing under real
operational conditions.
.PP
In a similar manner CCIR and CMTT have formulated media and
application orientated models for use in their studies. The following
recommendations describe the relevant models.
.RT
.LP
	\(em
	 Recommendation 502\(hy2 (Draft). Hypothetical Reference Circuit for Sound 
Programme Transmission. (Terrestrial systems and systems in the 
fixed\(hysatellite service).
.LP
	\(em
	 Recommendation 521\(hy1. Hypothetical Reference Digital Path for systems 
using digital transmission in the fixed\(hysatellite service. 
.LP
	\(em
	 Recommendation 556. Hypothetical Reference Digital Path for radio\(hyrelay 
systems for telephony. 
.ce 1000
ANNEX\ A
.ce 0
.ce 1000
(to Recommendation G.801)
.sp 9p
.RT
.ce 0
.ce 1000
\fBThe application of\fR 
\fBHypothetical Reference Models\fR 
.sp 1P
.RT
.ce 0
.ce 1000
\fBin the formulation of equipment design objectives\fR 
.ce 0
.PP
An important use of hypothetical reference models is to
facilitate
the apportionment of network performance objectives to constituent elements,
prior to the derivation of equipment design objectives. To satisfactorily
achieve this objective a diagrammatic representation of the approach adopted 
by CCITT in the formulation of equipment design objectives is shown in 
Figure\ A\(hy1/G.801.
.sp 1P
.RT
.PP
The approach recognizes that it may be necessary to derive from
the
\*Qstandard HRX\*U a more appropriate HRX which better takes into account 
both the usage and the specific network performance parameter under study. 
The adoption of this approach will facilitate the formulation of rules 
governing the use of certain digital elements such as satellite links, 
transcoders, digital 
pads,\ etc.
.PP
National Administrations are advised to develop their own
representative network models reflecting the features of their evolving
national digital network in order to validate prima facie compliance with
international standards.
.bp
.RT
.LP
.rs
.sp 32P
.ad r
\fBFIGURE A\(hy1/G.801, p.5\fR 
.sp 1P
.RT
.ad b
.RT
.sp 2P
.LP
\fBRecommendation\ G.802\fR 
.RT
.sp 2P
.ce 1000
\fBINTERWORKING\ BETWEEN\ NETWORKS\fR 
.EF '%	Fascicle\ III.5\ \(em\ Rec.\ G.802''
.OF '''Fascicle\ III.5\ \(em\ Rec.\ G.802	%'
.ce 0
.sp 1P
.ce 1000
\fBBASED\ ON\ DIFFERENT\ DIGITAL\ HIERARCHIES\ AND\ SPEECH\ ENCODING\ LAWS\fR 
.ce 0
.sp 1P
.ce 1000
\fI(former Recommendations G.722 of Volume III of\fR 
.sp 9p
.RT
.ce 0
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.ce 1000
\fIthe Yelow Book, further amended)\fR 
.ce 0
.sp 1P
.LP
\fB1\fR 	\fBIntroduction\fR 
.sp 1P
.RT
.PP
This Recommendation deals with the following aspects of
interworking between networks for transport of 64\ kbit/s digital
information:
.RT
.LP
	\(em
	encoding law and conversion rule for interworking between
networks using the different encoding laws based on Recommendations\ G.711,
G.721 and\ G.722;
.LP
	\(em
	 interworking hierarchy between networks which incorporate the different 
digital hierarchies based on Recommendation\ G.702; 
.LP
	\(em
	 interworking arrangements between networks incorporating the different 
hierarchies and encoding laws; and, 
.LP
	\(em
	 interconnection by plesiochronous operation between networks which each 
has an independent synchronization. 
.bp
.PP
This Recommendation is applicable also to ISDNs for transport of B\ channels 
specified in Recommendation\ I.412. 
.PP
\fINote\fR \ \(em\ The future specifications on channels and their bit 
rates to support ISDN broadband services for customer\(hyto\(hycustomer 
applications may 
require additional interworking arrangement specifications other than those
specified below.
.RT
.sp 2P
.LP
\fB2\fR 	\fBTerms and definitions\fR 
.sp 1P
.RT
.PP
The terms used in this Recommendation and not defined below are
described in Recommendations\ G.701 or\ I.112.
.RT
.sp 1P
.LP
2.1
	\fBz\(hyoperation\fR 
.sp 9p
.RT
.PP
Conversion of the \(*m\(hylaw character signal \*Q00000000\*U (all\(hyzero
octet) into the \(*m\(hylaw character signal \*Q00000010\*U, where \*Q1\*U 
is the bit 
numbered seven in the octet (see Recommendation\ G.711).
.PP
\fINote\fR \ \(em\ Bit number indicates the chronological order of transmission 
of bits in serial processing. 
.RT
.sp 1P
.LP
2.2
	\fB1.5/2 Mbit/s multiplex system conversion (1.5/2 Mbit/s MSC)\fR 
.sp 9p
.RT
.PP
A function which embodies the following properties:
.RT
.LP
	1)
	termination of a digital link operating at a digital
hierarchical level of 1544\ kbit/s;
.LP
	2)
	termination of a digital link operating at a digital
hierarchical level of 2048\ kbit/s; and,
.LP
	3)
	 rearrangement of 64 kbit/s channels between 1544\ kbit/s and 2048\ kbit/s 
digital terminations. 
.PP
\fINote\fR \ \(em\ The hierarchical levels and the frame structures are
specified in Recommendations\ G.702 and\ G.704, respectively.
.sp 1P
.LP
2.3
	\fBpulse density requirement (PDR) at 1544 kbit/s\fR 
.sp 9p
.RT
.PP
The minimum requirement for an entire 1544 kbit/s digital signal is that 
there should be no more than 15\ binary \*Q0\*Us between successive binary 
\*Q1\*Us and that there should be an average binary \*Q1\*Us density of 
at least one in every eight bits. This requirement is due to the design 
of a number of existing systems (see Recommendation\ G.703.) 
.PP
Moreover, the requirement for an octet\(hystructured source in a
1544\ kbit/s digital link is that at least one binary \*Q1\*U should be 
contained in any octet. 
.RT
.sp 2P
.LP
\fB3\fR 	\fBUnrestricted 64 kbit/s transfer capability of a digital\fR 
\fBlink\fR 
.sp 1P
.RT
.PP
Newly introduced digital transmission systems should have the
capability to provide bit sequence independence for 64\ kbit/s digital links.
This capability should be activated as soon as unrestricted 64\ kbit/s 
transfer capability can be practically realized. 
.PP
During a transition period, however, 56 kbit/s bit sequence
independent transfer capability may be provided by bilateral agreement.
(Important constraints on the data formats transmitted by source data terminal 
equipment are given in Annex\ 1 to this Recommendation.) 
.RT
.sp 2P
.LP
\fB4\fR 	\fBEncoding law conversion between A\(hylaw and \(*m\(hylaw\fR 
.sp 1P
.RT
.sp 1P
.LP
4.1
	\fIEncoding law on an international digital link\fR 
.sp 9p
.RT
.PP
International digital links between countries which have adopted
different PCM encoding laws (A\(hylaw or \(*m\(hylaw) should carry signals 
encoded in 
accordance with the A\(hylaw specified in Recommendation\ G.711.
.PP
Where both countries have adopted the same law, that law should be
used on digital links between them.
.bp
.RT
.sp 1P
.LP
4.2
	\fIConversion rule\fR 
.sp 9p
.RT
.PP
A\(hylaw/\(*m\(hylaw conversion necessary between countries which have
adopted different PCM encoding laws will be performed according to
Recommendation\ G.711 by the \(*m\(hylaw country. The conversion includes 
the even\(hybit inversion of the A\(hylaw character signal. 
.PP
\fINote\fR \ \(em\ Location of the conversion function in a \(*m\(hylaw 
country is a national matter depending upon the structure of domestic digital 
networks, and is left to the discretion of the Administrations in the \(*m\(hylaw 
country. 
.RT
.sp 1P
.LP
4.3
	\fIControl of conversion function\fR 
.sp 9p
.RT
.PP
In switched public network applications enabling/disabling of the conversion 
function should be under control of the international switching 
system, and will be carried out on a call\(hyby\(hycall or during\(hya\(hycall 
basis 
depending upon the service category requested by the signalling protocol.
.PP
It should also be possible to enable/disable this conversion function manually 
and/or via an operator terminal on a per\(hychannel or semi\(hypermanent 
basis. This capability would be necessary for configuring leased line circuits 
not passing through the international switching system, or if the international 
switching system were not capable of controlling this function. 
.PP
\fINote\fR \ \(em\ Control of conversion function in ISDN environment is
specified in I.300\(hyseries and I.500\(hyseries Recommendations.
.RT
.sp 2P
.LP
\fB5\fR 	\fBInterworking hierarchy\fR 
.sp 1P
.RT
.PP
For international interworking between networks using different
digital hierarchies specified in Recommendation\ G.702, the following
interworking hierarchy should be employed:
.PP
2048 | (em | 312 | (em | 4 | 36 | (em | 39 | 64\ kbit/s.
.PP
For interworking between networks with different digital
hierarchies but with 1544\ kbit/s primary level, however, levels other than
those specified for the above interworking hierarchy may be employed
(e.g.\ 1544\ kbit/s).
.PP
\fINote\ 1\fR \ \(em\ National networks with a 1544 kbit/s primary level may
offer transit of international traffic of 6312\ kbit/s composed of three
2048\ kbit/s signals or of 44 | 36\ kbit/s containing twenty\(hyone 2048\ 
kbit/s 
signals. These networks will provide the property of bit sequence independence 
at 6312\ and 44 | 36\ kbit/s and hence at 2048\ kbit/s. 
.PP
\fINote\ 2\fR \ \(em\ The frame structures for 2048\(hy6312 kbit/s, 6312\(hy44 | 36 
kbit/s and 44 | 36\(hy139 | 64\ kbit/s multiplexing stages are specified in
Recommendations\ G.747, G.752 and\ G.755, respectively.
.RT
.sp 2P
.LP
\fB6\fR 	\fBInterworking arrangements\fR 
.sp 1P
.RT
.PP
Based on the general specifications described in the previous
Sections, establishment of an international digital interconnection between
networks using the different digital hierarchies and speech encoding laws
should conform to the interworking arrangements specified in
Table\ 1/G.802.
.RT
.sp 2P
.LP
\fB7\fR \fBTransport of a 1544 kbit/s signal within a G.704\(hystructured\fR 
\fB2048 kbit/s signal\fR 
.sp 1P
.RT
.PP
For international leased line applications, the transmission of
1544 kbit/s signals may be considered using a special mapping into
point\(hyto\(hypoint 2048\ kbit/s signals. Annex\ B to this Recommendation 
specifies 
the method for this mapping.
.PP
\fINote\fR \ \(em\ The possible development of specific mappings of 8448 or
34 | 68\ kbit/s signals into 44 | 36\ kbit/s signals is not precluded.
.RT
.sp 2P
.LP
\fB8\fR 	\fBSynchronization of an international digital link\fR 
.sp 1P
.RT
.sp 1P
.LP
8.1
	\fILinks not synchronized to the national networks\fR 
.sp 9p
.RT
.PP
Where independently synchronized national networks are
interconnected via an international digital link, the timing of which is
independent of the national networks, the link should be operated in a
plesiochronous mode with the accuracy specified in Recommendation\ G.811.
.RT
.sp 1P
.LP
8.2
	\fILinks synchronized to the network in the transmitting country\fR 
.sp 9p
.RT
.PP
Where independently synchronized national networks are
interconnected via an international digital link, the timing of which is
synchronized to the national network in the transmitting country, the
plesiochronous operation will be performed in the receiving
country.
.bp
.RT
.ce
\fBH.T. [T1.802]\fR 
.ce
TABLE\ 1/G.802
.ce
\fBInterworking arrangements\fR 
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
cw(48p) | cw(108p) | cw(36p) | cw(36p) .
Type of information	Voice or voiceband data	Non\(hyvoice information	 {
Signalling information
(Note 1)
 }
_
.T&
lw(48p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) | cw(36p) .
 {
Encoding
law at IRP
(Note 2)
Function
 }	PCM  G.711	ADPCM  G.721	SB\(hyADPCM  G.722	\(hy\(hy\(hy\(hy\(hy\(hy	\(hy\(hy\(hy\(hy\(hy\(hy
.TE
.TS
center box ;
lw(48p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) | cw(18p) .
Network (Note 3)	A	B	A	B	A	B	A	B	A	B
_
1.5/2 Mbit/s  MSC	\(em	X	\(em	X	\(em	X	\(em	X	\(em	X
_
A/\(*m and \(*m/A  conversion	\(em	X	\(em	\(em	\(em	\(em	\(em	\(em	\(em	\(em
_
Z\(hyoperation	\(em	X  (Note 4)	\(em	X  (Notes 4 and 5)	\(em	X  (Notes 4 and 6)	\(em	X  (Note 4)	\(em	\(em
_
Transcoding	\(em	\(em	X	X	\(em	\(em	\(em	\(em	\(em	\(em
.TE
.LP
\fINote\ 1\fR
\ \(em\ Signalling information is transferred on unrestricted channels
between International Switching Centers (ISCs).
.LP
\fINote\ 2\fR
\ \(em\ IRP = Interworking reference point between Network A and
Network B.
.LP
\fINote\ 3\fR
\ \(em\ \*QA\*U is a network within the country incorporating the A\(hylaw and
2048\ kbit/s\(hybased digital hierarchy. \*QB\*U is a network within the country
incorporating the \(*m\(hylaw and 1544\ kbit/s\(hybased digital hierarchy.
.LP
\fINote\ 4\fR
\ \(em\ Z\(hyoperation in the \(*m\(hylaw country will be applied when the link in
that country contains transmission systems that have to meet PDR; in this
case unrestricted 64\ kbit/s transfer capability cannot be provided due to
PDR and the bit sequence independent transfer capability is restricted to
56\ kbit/s.
.LP
\fINote\ 5\fR
\ \(em\ 32\ kbit/s digital signals, which are voice or voiceband data
signals encoded in accordance with the ADPCM algorithm specified in
Recommendation\ G.721, do not contain a \*Q0000\*U code word.
(See Recommendation\ G.721.) This implies that even when PDR exists in the
\(*m\(hylaw country, these signals will not be affected by the z\(hyoperation and
will be transferred transparently.
.LP
\fINote\ 6\fR
\ \(em\ 64\ kbit/s audio signals, where the audio signals having the
bandwidth of 50 to 7000\ Hz are encoded at 64, 56 or 48\ kbit/s in
accordance with the coding algorithm specified in
Recommendation\ G.722, do not contain an all\(hyzero octet.
(See Recommendation\ G.722.) This implies that even when PDR exists in the
\(*m\(hylaw country, these signals will not be affected by the z\(hyoperation and
will be transferred transparently.
.nr PS 9
.RT
.ad r
\fBTableau 1/G.802 [T1.802], p.\fR 
.sp 1P
.RT
.ad b
.RT
.LP
.sp 7
.bp
.ce 1000
ANNEX\ A
\v'6p'
.ce 0
.ce 1000
(to Recommendation G.802)
\v'6p'
.sp 9p
.RT
.ce 0
.ce 1000
\fBImpact on terminal equipment designed to work with 56\ kbit/s\fR 
.sp 1P
.RT
.ce 0
.ce 1000
\fBbit sequence independent transfer capability\fR \v'1P'
.ce 0
.PP
During a transition period 56 kbit/s bit sequence independent
transfer capability may be provided by bilateral agreement. In this case a
56\ kbit/s bit sequence independent transfer capability requires that the 
source data terminal equipment\ (DTE) fix the eighth bit of each octet 
to binary \*Q1\*U. This must be done on both ends of the digital connection 
even if one portion of the connection has unrestricted 64\ kbit/s transfer 
capability. Failure to keep the eighth bit fixed to binary \*Q1\*U will 
cause any all\(hyzero octet to be 
converted to \*Q00000010\*U by z\(hyoperation in the \(*m\(hylaw country.
\v'2P'
.sp 1P
.RT
.ce 1000
ANNEX\ B
\v'6p'
.ce 0
.ce 1000
(to Recommendation G.802)
\v'6p'
.sp 9p
.RT
.ce 0
.ce 1000
\fBMapping method of a 1544 kbit/s signal\fR 
.sp 1P
.RT
.ce 0
.ce 1000
\fBinto a G.704\(hystructured 2048 kbit/s signal\fR \v'1P'
.ce 0
.PP
The following is a means of accommodating a bit synchronous 1544 kbit/s 
signal, which may be unstructured or structured, within a 
G.704\(hystructured 2048 kbit/s frame, for the purpose of providing leased line
applications at 1544\ kbit/s only. The 1544\ kbit/s signal is transmitted
transparently without regard to its frame structure within the 2048\ kbit/s
signal.
.sp 1P
.RT
.PP
The 193 bits of an arbitrary 125 \(*ms period of the 1544 kbit/s
signal should be accommodated within a G.704\(hystructured 2048\ kbit/s 
frame as 
follows:
.LP
	TS\ 0:
	Frame alignment signal according to Recommendation\ G.704
.LP
	TS \ 1\(hy15
	
.LP
	TS 17\(hy25
		193 contiguous bits of the 1544 kbit/s signal
.LP
	Bit 1 in TS 26
	
.LP
	TS 16, 27\(hy31:
	Reserved for possible accommodation of additional
information at up to 384\ kbit/s (Note\ 2)
.PP
\fINote\ 1\fR \ \(em\ In cases where only the 1544 kbit/s signal is to be
transported, the timing of the 1544 kbit/s (or 2048\ kbit/s) outgoing signal
should be derived from the 2048\ kbit/s (or 1544\ kbit/s) incoming signal for
each direction of transmission.
.PP
\fINote\ 2\fR \ \(em\ In some cases, e.g. where information is transported 
by the reserved time\(hyslots, the timing of the outgoing signal should 
be traceable to the national reference clock conforming to Recommendation\ 
G.811. This will 
require the use of 125\ \(*ms slip buffers.
.PP
\fINote\ 3\fR \ \(em\ The maximum capacity available to end\(hyusers for 
transparent transport of their information is 1536\ kbit/s and not 1544\ 
kbit/s. Depending on the national regulations some network operators may 
offer the user of part of the 8\ kbit/s overhead associated with a 1544\ 
kbit/s signal for performance 
monitoring and its reporting.
.bp
.RT
.IP
\fB8.1\ \fR \fBDesign objectives for digital networks\fR 
.sp 1P
.RT
.sp 2P
.LP
\fBRecommendation\ G.810\fR 
.RT
.sp 2P
.sp 1P
.ce 1000
\fBCONSIDERATIONS\ ON\ TIMING\ AND\ SYNCHRONIZATION\ ISSUES\fR 
.EF '%	Fascicle\ III.5\ \(em\ Rec.\ G.810''
.OF '''Fascicle\ III.5\ \(em\ Rec.\ G.810	%'
.ce 0
.sp 1P
.ce 1000
\fI(Melbourne, 1988)\fR 
.sp 9p
.RT
.ce 0
.sp 1P
.LP
\fB1\fR 	\fBGeneral\fR 
.sp 1P
.RT
.PP
This Recommendation provides information and guidance concerning
the various timing and synchronization Recommendations as well as insight 
into the fundamental related issues. 
.RT
.sp 2P
.LP
\fB2\fR 	\fBDefinitions\fR 
.sp 1P
.RT
.sp 1P
.LP
	\fBprimary reference clock\fR 
.sp 9p
.RT
.PP
A reference clock that provides a timing signal with long term
frequency departure maintained at 1 | (mu | 0\uD\dlF261\u1\d\u1\d or better 
with 
verification to Universal Time Coordinated\ (UTC). Requirements for primary
reference clocks are given in Recommendation\ G.811.
.PP
\fINote\ 1\fR \ \(em\ The primary reference clock may generate a timing signal
completely autonomous of other references or alternatively, the primary
reference clock may not have a completely autonomous implementation, in 
which case it may employ direct control from standard UTC\(hyderived frequency 
and time sources. 
.PP
\fINote\ 2\fR \ \(em\ This clock is sometimes referred to as a Stratum 1 clock
(i.e.\ the highest quality clock in the network).
.RT
.sp 1P
.LP
	\fBsynchronous network node\fR 
.sp 9p
.RT
.PP
A geographical location at which there are one or more
interconnected synchronous digital equipments.
.RT
.sp 1P
.LP
	\fBtransit node\fR 
.sp 9p
.RT
.PP
A synchronous network node which interfaces with other nodes and does not 
directly interface with customer equipment. 
.RT
.sp 1P
.LP
	\fBlocal node\fR 
.sp 9p
.RT
.PP
A synchronous network node which interfaces directly with
customer equipment.
.RT
.sp 1P
.LP
	\fBslave clock\fR 
.sp 9p
.RT
.PP
A clock whose timing output is phase\(hylocked to the timing
signal received from a higher quality clock. Requirements for slave
clocks are given in Recommendation\ G.812.
.PP
\fINote\fR \ \(em\ The highest quality slave clock is sometimes referrred 
to as a transit node clock, or a Stratum\ 2 clock. The second highest quality 
slave 
clock is sometimes referred to as a local node clock, or a Stratum\ 3
clock.
.RT
.sp 1P
.LP
	\fBjitter\fR 
.sp 9p
.RT
.PP
Short\(hyterm variations of the significant instants of a digital
signal from their reference positions in time.
.RT
.sp 1P
.LP
	\fBtiming jitter\fR 
.sp 9p
.RT
.PP
The short term variations of the significant instants of a digital signal 
from their ideal positions in time (where short term implies these 
variations are of frequency greater than or equal to 10\ Hz).
.bp
.RT
.sp 1P
.LP
	\fBalignment jitter\fR 
.sp 9p
.RT
.PP
The short term variations between the optimum sampling instants of a digital 
signal and a sampling clock derived from it. 
.RT
.sp 1P
.LP
	\fBwander\fR 
.sp 9p
.RT
.PP
The long term variations of the significant instances of a digital signal 
from their ideal positions in time (where long term implies that these 
variations are of frequency less than 10\ Hz). 
.PP
\fINote\fR \ \(em\ For the purposes of this Recommendation and the following
related Recommendations, this definition of wander does not include integrated 
frequency departure. 
.RT
.sp 1P
.LP
	\fBfrequency departure\fR 
.sp 9p
.RT
.PP
An underlying offset in the long term frequency of a timing signal from 
its ideal frequency. 
.RT
.sp 1P
.LP
	\fBslip\fR 
.sp 9p
.RT
.PP
The repetition or deletion of a block of bits in a synchronous or plesiochronous 
bit stream due to a discrepancy in the read and write rates at a buffer. 
.RT
.sp 2P
.LP
\fB3\fR 	\fBDescription of\fR 
\fBphase variation components\fR 
.sp 1P
.RT
.PP
Phase variation is commonly separated into three components:
jitter, wander and integrated frequency departure. In addition, phase
discontinuities due to transient disturbances such as network re\(hyrouting,
automatic protection switching,\ etc., may also be a source of phase
variation.
.RT
.LP
\fB4\fR 	\fBImpairments caused by phase variation\fR 
.sp 1P
.RT
.sp 2P
.LP
4.1
	\fITypes of impairments\fR 
.sp 1P
.RT
.sp 1P
.LP
4.1.1
	\fIErrors\fR 
.sp 9p
.RT
.PP
Errors may occur at points of signal regeneration as a result of
timing signals being displaced from their optimum positions in time.
.RT
.sp 1P
.LP
4.1.2
	\fIDegradation of digitally encoded analogue information\fR 
.sp 9p
.RT
.PP
Degradation of digitally encoded analogue information may occur as a result 
of phase variation of the reconstructed samples in the digital to 
analogue conversion device at the end of the connection. This may have
significant impact on digitally encoded video signals.
.RT
.sp 1P
.LP
4.1.3
	\fISlips\fR 
.sp 9p
.RT
.PP
Slips arise as a result of the inability of an equipment buffer
store (and/or other mechanisms) to accommodate differences between the 
phases and/or frequencies of the incoming and outgoing signals in cases 
where the 
timing of the outgoing signal is not derived from that of the incoming 
signal. Slips may be controlled or uncontrolled depending on the slip control 
strategy.
.RT
.sp 2P
.LP
4.2
	\fIControl of impairments\fR 
.sp 1P
.RT
.sp 1P
.LP
4.2.1
	\fIErrors\fR 
.sp 9p
.RT
.PP
The intent of both network and equipment jitter specifications is to ensure 
that jitter has no impact on the error performance of the 
network.
.RT
.sp 1P
.LP
4.2.2
	\fIDegradation of digitally encoded analogue signals\fR 
.sp 9p
.RT
.PP
The intent of jitter specifications is to provide sufficient
information to enable equipment designers to accommodate the expected levels 
of phase variation without incurring unacceptable degradations. 
.bp
.RT
.sp 1P
.LP
4.2.3
	\fISlips\fR 
.sp 9p
.RT
.PP
Slips may occur in asynchronous multiplexes and various synchronous equipments. 
Given the specified levels of phase variation, slip occurrences may be 
minimised in asynchronous muldexes by appropriate choice of justification 
and muldex buffer capacity within. For synchronous equipments, slip occurrences 
may be minimised by appropriate choice of buffer capacity as well as rigorous 
specification of clock performance. 
.PP
It should be noted that it is impossible to eliminate slips when there 
is a frequency difference between the incoming and outgoing timing signals. 
Controlled slip performance objectives for an international connection are
given in Recommendation\ G.822.
.PP
Various forms of aligning equipment may be used to minimise the impact 
of slips. The following two forms of aligning equipment are suitable for 
the 
termination of digital signals:
.RT
.LP
	\(em
	frame aligner
;
.LP
	\(em
	time\(hyslot aligner
.
.sp 1P
.LP
4.2.3.1\ \ Where a frame aligner is used, a slip will consist of the insertion 
or removal of a consecutive set of digits amounting to a frame. In the 
case of frame structures defined in Recommendation\ G.704 the slip can 
consist of one 
complete frame. It is of importance that the maximum and mean delays introduced 
by the frame aligner should be as small as possible in order to minimize 
delay. It is also of importance that, after the frame aligner has produced 
a slip, it should be capable of absorbing substantial further changes in 
the arrival time of the frame alignment signals before a further slip is 
necessary. 
.sp 9p
.RT
.LP
4.2.3.2\ \ Where a slot aligner is used, a slip will consist of the insertion 
or removal of eight consecutive digit positions of a channel time slot 
in one or more 64\ kbit/s channels. Because slips may occur on different 
channels at 
different times, special control arrangements will be necessary in switches 
if octet sequence integrity of multiple time\(hyslot services is to be 
maintained. 
.sp 2P
.LP
\fB5\fR 	\fBPurpose of phase variation specifications\fR 
.sp 1P
.RT
.sp 1P
.LP
5.1
	\fIJitter\fR 
.sp 9p
.RT
.PP
Jitter requirements given in Recommendations G.823 and G.824 fall into 
two basic categories: 
.RT
.LP
	\(em
	specification of the maximum permissible jitter at the
output of hierarchical interfaces;
.LP
	\(em
	sinusoidal jitter stress test specifications to ensure the
input ports can accommodate expected levels of network jitter.
.PP
Additional jitter requirements for individual equipments may be
found in the appropriate equipment Recommendations.
.sp 1P
.LP
5.2
	\fIWander\fR \fIand long term frequency departure\fR 
.sp 9p
.RT
.PP
Relevant wander requirements fall into the following
categories:
.RT
.LP
	i)
	maximum permissible wander at the output of synchronous
network nodes;
.LP
	ii)
	stress tests to ensure that synchronous equipment input
ports can accommodate expected levels of network wander;
.LP
	iii)
	wander specifications for primary reference and slave
clocks may include:
.LP
	a)
	intrinsic output wander under ideal conditions;
.LP
	b)
	intrinsic output wander under free\(hyrunning conditions;
.LP
	c)
	output wander under stress test conditions;
.LP
	d)
	wander transfer characteristic.
.PP
The purpose of these Recommendations is not only to provide limits for 
the allowance wander accumulation along the transmission paths but also 
for the wander accumulation along the synchronization distribution paths 
arising 
from cascaded clocks.
.bp
.sp 2P
.LP
\fB6\fR 	\fBStructure of synchronization networks\fR 
.sp 1P
.RT
.sp 1P
.LP
6.1
	\fISynchronization modes\fR 
.sp 9p
.RT
.PP
International networks usually work in the plesiochronous mode one with 
another. 
.PP
The synchronization of national networks may be of the following
types:
.RT
.LP
	\(em
	fully synchronized
, controlled by one or several
primary reference clocks;
.LP
	\(em
	fully plesiochronous
;
.LP
	\(em
	 mixed, in which synchronized sub\(hynetworks are controlled by one or 
several primary reference clocks functioning plesiochronously one with 
another. 
.sp 1P
.LP
6.2
	\fISynchronization networks\fR 
.sp 9p
.RT
.PP
There are two fundamental methods of synchronizing nodal
clocks:
.RT
.LP
	\(em
	master\(hyslave synchronization
;
.LP
	\(em
	mutual synchronization
.
.PP
The master\(hyslave synchronization system has a single primary
reference clock to which all other clocks are phase\(hylocked. Synchronization 
is achieved by conveying the timing signal from one clock to the next clock. 
Hierarchies of clocks can be established with some clocks being slaved from
higher order clocks and in turn acting as master clocks for lower order
clocks.
.PP
In a mutual synchronization system, all clocks are interconnected;
there is no underlying hiearchical structure or unique primary reference
clock.
.PP
Some practical synchronization strategies combine master\(hyslave and
mutual synchronization techniques.
.RT
.sp 2P
.LP
\fBRecommendation\ G.811\fR 
.RT
.sp 2P
.ce 1000
\fBTIMING\ REQUIREMENTS\ AT\ THE\ OUTPUTS\ OF\ PRIMARY\ REFERENCE | fR 
\fBCLOCKS\ SUITABLE\ FOR\fR 
.EF '%	Fascicle\ III.5\ \(em\ Rec.\ G.811''
.OF '''Fascicle\ III.5\ \(em\ Rec.\ G.811	%'
.ce 0
.sp 1P
.ce 1000
\fBPLESICHRONOUS\ OPERATION\ OF\ INTERNATIONAL\ DIGITAL\ LINKS\fR 
.ce 0
.sp 1P
.ce 1000
\fI(Melbourne, 1988)\fR 
.sp 9p
.RT
.ce 0
.sp 1P
.LP
\fB1\fR 	\fBGeneral\fR 
.sp 1P
.RT
.sp 2P
.LP
1.1
	\fIInternational connections and network synchronization\fR 
\fIconsiderations\fR 
.sp 1P
.RT
.PP
National digital networks, which may have a variety of internal
synchronization arrangements, will usually be connected by international 
links which operate plesiochronously. International switching centres (ISCs) 
will be interconnected directly or indirectly via one or more intermediate 
ISCs, as 
indicated in the hypothetical reference connection (HRX) shown in
Figure\ 1/G.801.
.PP
International connections terminate on synchronous network nodes
that may or may not be co\(hylocated with a primary reference clock. Such 
network nodes may include slave clocks. Therefore, synchronous network 
node clock 
specifications are essential to ensure satisfactory operation of plesiochronous 
international digital links. 
.PP
Figure 1/G.811 illustrates the two alternative international
connections described above.
.bp
.RT
.LP
.rs
.sp 30P
.ad r
\fBFigure 1/G.811, p.\fR 
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
1.2
	\fIPurpose of this Recommendation\fR 
.sp 9p
.RT
.PP
The purpose of this Recommendation is to specify requirements for primary 
reference clocks, promote understanding of associated timing 
requirements for plesiochronous operation of international digital links, 
and to clarify the relationship of the requirements for synchronous network 
nodes, constituent clocks and the use of satellite systems. 
.PP
Administrations may apply this Recommendation, at their own
discretion, to primary reference clocks other than those used in connection
with international traffic.
.RT
.sp 1P
.LP
1.3
	 \fIInteraction between plesiochronous and synchronous international\fR 
\fIoperation\fR 
.sp 9p
.RT
.PP
It is important that the Recommendations for plesiochronous
operation should not preclude the possibility of the later introduction of
international synchronization.
.PP
When plesiochronous and synchronous operations coexist within the
international network, the nodes will be required to provide for both types 
of operation. It is therefore important that the synchronization controls 
do not cause short\(hyterm frequency departures of the clocks which are 
unacceptable for plesiochronous operation. The magnitudes of the short\(hyterm 
frequency departures should satisfy the specifications in \(sc 2.2. 
.bp
.RT
.sp 1P
.LP
1.4
	\fIMaximum time interval error and relationship with frequency\fR 
\fIdeparture\fR 
.sp 9p
.RT
.PP
Maximum time interval error (MTIE) is the maximum peak\(hyto\(hypeak
variation in the time delay of a given timing signal with respect to an 
ideal timing signal within a particular time period (Figure\ 2/G.811), 
i.e. 
MTIE(\fIS\fR )\ =\ max\ \fIx\fR (\fIt\fR )\(hymin \fIx\fR (\fIt\fR ) for 
all \fIt\fR 
within\ \fIS\fR .
.RT
.LP
.rs
.sp 17P
.ad r
\fBFigure 2/G.811, p.\fR 
.sp 1P
.RT
.ad b
.RT
.PP
Long\(hyterm frequency departure (?63
\fIf\fR /\fIf\fR )
is determined by the MTIE divided by the observation interval\ \fIS\fR ,
as\ \fIS\fR increases.
.PP
\fINote\fR \ \(em\ The rigorous definition and measurement of long\(hyterm
frequency departure for clocks is a subject for further study.
.RT
.sp 2P
.LP
\fB2\fR 	\fBLong\(hyterm frequency departure and phase stability of primary
reference clocks\fR 
.sp 1P
.RT
.PP
A primary reference clock controls the synchronization performance of the 
overall network. It is necessary to specify the long\(hyterm frequency 
departure and phase stability of a primary reference clock, and to provide
guidance concerning issues associated with degradation and unavailability
performance. The definition of a primary reference clock is given in
Recommendation\ G.810.
.RT
.sp 1P
.LP
2.1
	\fILong\(hyterm frequency departure\fR 
.sp 9p
.RT
.PP
A primary reference clock should be designed for a long\(hyterm
frequency departure of not greater than\ 1\ \(mu\ 10\uD\dlF261\u1\d\u1\d. 
The long\(hyterm 
frequency departure of 1\ \(mu\ 10\uD\dlF261\u1\d\u1\d is about two orders 
of magnitude 
larger than the uncertainty of Coordinated Universal Time (UTC). Therefore
UTC should be the reference for long\(hyterm frequency departure (see CCIR
Report\ 898).
.PP
The theoretical long\(hyterm mean rate of occurrence of controlled
frame or octet slips (i.e.\ the design rate of slips based on ideally
undisturbed conditions) in any 64\ kbit/s channel is consequently not greater
than one in 70\ days per digital international link (see
Recommendation\ G.822).
.PP
\fINote\ 1\fR \ \(em\ Some Administrations support a primary reference clock
long\(hyterm frequency departure of not greater than\ 7\ \(mu\ 10\uD\dlF261\u1\d\u2\d 
based 
upon current primary reference clock technology.
.PP
\fINote\ 2\fR \ \(em\ Caesium\(hybeam technology is suitable for primary
reference clocks complying with the above specification.
.bp
.RT
.sp 1P
.LP
2.2
	\fIPhase stability\fR 
.sp 9p
.RT
.PP
The phase stability of a clock can be described by its phase
variations, which in turn can be separated into a number of
components:
.RT
.LP
	\(em
	phase discontinuities due to transient disturbances;
.LP
\fR 	\(em
	long\(hyterm phase variations (wander and integrated frequency
departure);
.LP
	\(em
	short\(hyterm phase variations (jitter).
.PP
A phase stability model for primary reference clocks is described in the 
annex to this Recommendation. 
.sp 1P
.LP
2.2.1
	\fIPhase discontinuities\fR 
.sp 9p
.RT
.PP
Primary reference clocks need a very high reliability and are
likely to include replication of the equipment in order to ensure the
continuity of output. However, any phase discontinuity, due to internal
operations within the clock, should only result in a lengthening or shortening 
of the timing signal interval and must not cause a phase discontinuity 
in 
excess of 1/8 of a unit interval at the clock output. (This refers to output
signals at 1544\ kbit/s or 2048\ kHz, see \(sc\ 4. Specification of other 
interfaces is under study.) 
.RT
.sp 1P
.LP
2.2.2
	\fILong\(hyterm phase variations\fR 
.sp 9p
.RT
.PP
The maximum permissible long\(hyterm phase variation of the output of a 
primary reference clock (whether sinusoidal or pulse) is expressed in MTIE. 
.PP
The MTIE over a period of \fIS\fR seconds shall not exceed the following 
limits: 
.RT
.LP
	a)
	100 \fIS\fR \ ns
	for the interval 0.05 < \fIS\fR \(= 5
.LP
	b)
	(5 \fIS\fR + 500)\ ns
	for the interval 5 < \fIS\fR \(= 500
.LP
\fR 
	c)
	(0.01 \fIS\fR + \fIX\fR  | \ ns
	for values of \fIS\fR > 500.
.PP
The asymptote designated 10\uD\dlF261\u1\d\u1\d refers to the
long\(hyterm frequency departure specified in \(sc\ 2.1.
.PP
The value of \fIX\fR is under study. It is provisionally recommended that 
\fIX\fR \ =\ 3000\ ns. Certain Administrations support a value of 1000\ 
ns. 
.PP
\fINote\ 1\fR \ \(em\ For measurement of long\(hyterm phase variations, the use
of a 10\ Hz low\(hypass filter is suggested.
.PP
\fINote\ 2\fR \ \(em\ The MTIE Recommendation requires further study.
.PP
\fINote\ 3\fR \ \(em\ The overall specification is illustrated in
Figure\ 3/G.811.
.RT
.sp 1P
.LP
2.2.3
	\fIShort\(hyterm phase variations\fR 
.sp 9p
.RT
.PP
Clock implementations exist today which may have some
high\(hyfrequency phase instability components. The specification of maximum
permissible short\(hy term phase variation of a primary reference clock due to
jitter is under study.
.RT
.sp 2P
.LP
\fB3\fR 	\fBDegradation of the performance of a primary reference clock\fR 
.sp 1P
.RT
.PP
\fR 
To achieve the required high reliability a primary reference clock includes 
redundancy, i.e.\ by incorporating several (caesium beam) oscillators, 
the output of only one of these being used at any given time. If a clock 
frequency departs significantly from its nominal value, this should be 
detected and switching to an undegraded oscillator should then be effected. 
This 
switching should be accomplished before the MTIE specification is exceeded.
.PP
\fR With current technology, the performance of a primary reference
clock is statistically well below the MTIE specification of
Figure\ 3/G.811.
.RT
.sp 2P
.LP
\fB4\fR 	\fBInterfaces\fR 
.sp 1P
.RT
.PP
The preferred interface for the timing output is in accordance with Recommendation\ 
G.703, \(sc\ 10, i.e.\ an interface at 2048\ kHz. By agreement between 
operators or manufacturers of equipment, the timing signal may also be 
delivered at various other physical interfaces (e.g., 1544\ kbitB/Fs primary 
rate signal, 1\ MHz, 5\ MHz, or 10\ MHz). 
.RT
.sp 2P
.LP
\fB5\fR \fBUse of satellite systems in an international plesiochronous 
digital network\fR 
.sp 1P
.RT
.PP
It is recommended that the link be operated in a plesiochronous
mode using high accuracy (1\ \(mu\ 10\uD\dlF261\u1\d\u1\d) source for the 
satellite TDMA 
timing. The international satellite links will be terminated on network 
nodes whose timing is in accordance with Recommendations\ G.823 and\ G.824. 
.bp
.RT
.LP
.rs
.sp 26P
.ad r
\fBFigure 3/G.811, p.9\fR 
.sp 1P
.RT
.ad b
.RT
.sp 2P
.LP
\fB6\fR 	\fBGuidelines concerning the measurement of jitter and wander\fR 
.sp 1P
.RT
.PP
\fR 
Verification of compliance with jitter and wander specifications
requires standardized measurement methodologies to eliminate ambiguities 
in the measurements and in interpretation and comparison of measurement 
results. 
Guidelines concerning the measurement of jitter and wander are contained in
Supplement No.\ 3.8 (O\(hySeries) and Supplement No.\ 35 at the end of this
Fascicle.
.RT
.ce 1000
ANNEX\ A
.ce 0
.ce 1000
(to Recommendation G.811)
.sp 9p
.RT
.ce 0
.ce 1000
\fBCharacterization of\fR 
\fB primary reference clock phase
stability\fR 
.sp 1P
.RT
.ce 0
.PP
The following phase stability model may be employed to
characterize primary reference clocks. Let \fIx\fR (\fIt\fR ) represent the
time interval error of a clock synchronized at \fIt\fR \ =\ 0, and free\(hyrunning 
against UTC thereafter. \fIx\fR (\fIt\fR ) may be defined as:
\v'6p'
.sp 1P
.RT
.ad r
.ad b
.RT
.LP
where:
.LP
	D
	is the normalized linear frequency drift per unit time
(ageing),
.LP
	\fIy\fR\d0\u	is the initial frequency departure with respect to UTC,
and
.LP
	\fIe\fR (\fIt\fR )
	is the random error component.
.bp
.PP
\fR 
The estimate of the standard deviation of \fIx\fR (\fIt\fR ) may be
obtained, and used for characterization of phase instability.
\v'6p'
.ad r
.ad b
.RT
.LP
where:
.LP
	\(*s
$$Ei:2:\fIy\fR _
	is the two\(hysample variance of the initial
frequency
departure, and
.LP
	\(*s
$$Ei:2:\fIy\fR _ (\(*t)
	is the two\(hysample Allan variance
describing the random frequency instability of the
clock.
.sp 2P
.LP
\fBRecommendation\ G.812\fR 
.RT
.sp 2P
.ce 1000
\fBTIMING\ REQUIREMENTS\ AT\ THE\ OUTPUTS\ OF\ SLAVE\ CLOCKS\ SUITABLE\ FOR\fR 
.EF '%	Fascicle\ III.5\ \(em\ Rec.\ G.812''
.OF '''Fascicle\ III.5\ \(em\ Rec.\ G.812	%'
.ce 0
.sp 1P
.ce 1000
\fBPLESIOCHRONOUS\ OPERATION\ OF\ INTERNATIONAL\ DIGITAL\ LINKS\fR 
.ce 0
.sp 1P
.ce 1000
\fI(Melbourne, 1988)\fR 
.sp 9p
.RT
.ce 0
.sp 1P
.LP
\fB1\fR 	\fBGeneral\fR 
.sp 1P
.RT
.sp 2P
.LP
1.1
	\fIPurpose of this Recommendation\fR 
.sp 1P
.RT
.PP
The purpose of this Recommendation is to specify requirements for slave 
clocks, and promote understanding of associated timing requirements for 
plesiochronous operation of international digital links. 
.PP
\fINote\fR \ \(em\ Administrations may apply this Recommendation, at their
own discretion, to slave clocks other than those used in connection with
international traffic. Supplement No.\ 35 gives guidance on one suitable 
method for the measurement of clock performance with respect to this 
Recommendation.
.RT
.sp 1P
.LP
1.2
	\fIMaximum relative time interval error\fR 
.sp 9p
.RT
.PP
The concept of maximum relative time interval error (MRTIE) is
useful in specifying slave clock performance. MRTIE is analogous to MTIE as
defined in Recommendation\ G.811 but with reference to a practical
high\(hyperformance oscillator instead of UTC.
.RT
.sp 2P
.LP
\fB2\fR 	\fBPhase stability of slave clocks\fR 
.sp 1P
.RT
.PP
The phase stability of a slave clock can be described by its phase variations 
which in turn can be separated into a number of 
components:
.RT
.LP
	\(em
	phase discontinuities due to transient disturbances;
.LP
\fR 
	\(em
	long\(hyterm phase variations (wander and integrated frequency
departure);
.LP
	\(em
	short\(hyterm phase variations (jitter).
.PP
A phase stability model for slave clocks is described in
Annex\ A to this Recommendation.
.sp 1P
.LP
2.1
	\fIPhase discontinuity\fR 
.sp 9p
.RT
.PP
In cases of infrequent internal testing or rearrangement operations within 
the slave clock, the following conditions should be met: 
.RT
.LP
\fR 
	\(em
	the phase variation over any period up to 2\u1\d\u1\d\ UI
should not exceed 1/8 of a UI;
.LP
	\(em
	for periods greater than 2\u1\d\u1\d UI in the phase
variation for each interval or 2\u1\d\u1\d\ 
UI should not exceed
1/8 UI up to a total amount of 1\ \(*ms,
.LP
Where the UI corresponds to the reciprocal of the bit rate of the
interface.
.bp
.sp 1P
.LP
2.2
	\fILong\(hyterm phase variations\fR 
.sp 9p
.RT
.PP
Slave clock phase stability requirements must account for clock
behaviour in real network environments. Impairments such as jitter, error
bursts, and outages are intrinsic characteristics of timing distribution
facilities. The following specifications are based on the slave clock phase
stability model contained in the Annex. This model characterizes actual 
clock performance, reflecting the stress conditions in real networks under 
which 
clocks should perform acceptably. There are three categories of clock operation 
which require specification: 
.RT
.LP
	i)
	ideal,
.LP
	ii)
	stressed, and
.LP
	iii)
	holdover.
.sp 1P
.LP
2.2.1
	\fIIdeal operation\fR 
.sp 9p
.RT
.PP
This category of operation reflects the performance of a clock
under conditions in which there are no impairments on the input timing
reference(s).
.PP
The MRTIE at the output of the slave clock should not, over any
period of \fIS\fR \ seconds, exceed the following provisional limits:
.RT
.LP
	1)
	0.05 < | fIS\fR < | 00: this region requires further study;
.LP
	2)
	1000 ns for \fIS\fR \(>=" | 00.
.PP
The resultant overall specification is summarized in
Figure\ 1/G.812.
.LP
.rs
.sp 24P
.ad r
\fBFigure 1/G.812, p.\fR 
.sp 1P
.RT
.ad b
.RT
.sp 1P
.LP
2.2.2
	\fIStressed operation\fR 
.sp 9p
.RT
.PP
This category of operation reflects the actual performance of a
clock considering the impact of real operating (stressed) conditions. Stressed 
conditions include the effects of jitter, protection switching activity, 
and 
error bursts. The result of such stressed conditions is timing impairments, 
as discussed in the Annex. 
.PP
The requirements for stressed operation are under study.
.bp
.RT
.sp 1P
.LP
2.2.3
	\fIHoldover operation\fR 
.sp 9p
.RT
.PP
This category of operation reflects the performance of a clock for the 
infrequent times when a slave clock will lose reference for a significant 
period of time. 
.PP
The MRTIE (see \(sc\ 1.2 and Recommendation\ G.811) at the output of
the slave clock should not, over any period of \fIS\fR \ seconds, exceed the
following provisional limits.
\v'6p'
.RT
.sp 1P
.ce 1000
For \fIS\fR \(>=" 100, MRTIE | \fIS\fR ) = (a\fIS\fR + 1/2 b\fIS\fR \u2\d 
+ \fIc\fR ) ns 
.ce 0
.sp 1P
.LP
.sp 1
where parameters a, b, c are proposed provisionally in Table 1/G.812
(Note\ 5):
.LP
.sp 2
.ce
\fBH.T. [T1.812]\fR 
.ce
TABLE\ 1/G.812
.ps 9
.vs 11
.nr VS 11
.nr PS 9
.TS
center box;
lw(24p) | cw(66p) | cw(66p) .
	 {
Transit node clock | ua\d\u)\d
(stratum 2 clock)
 }	 {
Local node clock | ua\d\u)\d
(stratum 3 clock)
 }
_
.T&
cw(24p) | cw(66p) | cw(66p) .
a	0.5 (Note 1)	10.0 (Note 3)
.T&
cw(24p) | cw(66p) | cw(66p) .
b	 {
1.16 \(mu 10\uD\dlF261\u5\d (Note 2)
 }	 {
2.3 \(mu 10\uD\dlF261\u4\d (Note 4)
 }
.T&
cw(24p) | cw(66p) | cw(66p) .
c	1000 (Note 6)	 {
1000 (Note 6)
 }
.TE
.LP
\ua\d\u)\d\ See Recommendation G.810 for definitions.
.LP
\fINote\ 1\fR
\ \(em\ Corresponds to un initial frequency offset of
5 \(mu 10\uD\dlF261\u1\d\u0\d.
.LP
\fINote\ 2\fR
\ \(em\ Corresponds to a frequency drift of
1 \(mu 10\uD\dlF261\u9\d/day.
.LP
\fINote\ 3\fR
\ \(em\ Corresponds to an initial frequency offset of
1 \(mu 10\uD\dlF261\u8\d.
.LP
\fINote\ 4\fR
\ \(em\ Corresponds to a frequency drift of
2 \(mu 10\uD\dlF261\u8\d/day.
.LP
\fINote\ 5\fR
\ \(em\ Temperature effects: the effect of changes in environmental
temperature on the performance of a slave clock in holdover mode requires
further study.
.LP
\fINote\ 6\fR
\ \(em\ Takes care of any MRTIE that might have existed at the
beginning of holdover operation, and of effects of internal configuration,
etc. in the clock (and timing distribution, if applicable). In any case,
a smooth transition between \*Qideal\*U and \*Qholdover\*U operations
is stipulated.
.nr PS 9
.RT
.ad r
\fBTableau 1/G.812 [T1.812], p.\fR 
.sp 1P
.RT
.ad b
.RT
.PP
.sp 2
The resultant overall specification is summarized in
Figure\ 2/G.812.
.sp 1P
.LP
2.3
	\fIShort\(hyterm phase variations\fR 
.sp 9p
.RT
.PP
Clock implementations exist which may have some high frequency
phase instability components. The maximum permissible short\(hyterm phase
variation of a slave clock due to jitter is under study.
.bp
.RT
.LP
.rs
.sp 28P
.ad r
\fBFigure 2/G.812, p.12\fR 
.sp 1P
.RT
.ad b
.RT
.ce 1000
ANNEX\ A
.ce 0
.ce 1000
(to Recommendation G.812)
.sp 9p
.RT
.ce 0
.ce 1000
\fBCharacterization of\fR 
\fBslave clock phase stability\fR 
.sp 1P
.RT
.ce 0
.PP
\fR A.1
The slave clock model is described by the following
equation:
\v'6p'
.sp 1P
.RT
.ad r
.ad b
.RT
.LP
where,
.LP
	\fIx\fR (\fIt\fR )
	is the phase\(hytime output relative to the
reference input (dimension time);
.LP
	y\db\\di\\da\\ds\u	is a residual fractional frequency offset
which can arise from disruption events on the reference
input (dimensionless);
.bp
.LP
	D
	is the linear frequency drift component when the clock is
in holdover condition (dimension 1/time);
.LP
	e\dp\\dm\u(\fIt\fR )
	is a white noise phase modulation (PM)
component associated with the short\(hyterm instability of the
clock (dimension time);
.LP
	e\df\\dm\u(\(*t)
	is a white noise fractional frequency
modulation
(FM) component associated with the disruption
process of the reference (dimensionless).
.PP
The clock model is best understood by considering the three
categories of clock operation:
.LP
	\(em
	ideal operation;
.LP
	\(em
	stressed operation;
.LP
	\(em
	holdover operation.
.sp 1P
.LP
A.1.1
	\fIIdeal operation\fR 
.sp 9p
.RT
.PP
For short observation intervals outside the tracking bandwidth of the PLL, 
the stability of the output timing signal is determined by the short term 
stability of the local synchronizer time base. In the absence of 
reference disruptions, the stability of the output timing signal behaves
asymptotically as a white noise PM process as the observation period is
increased to be within the tracking bandwidth of the PLL. The output of the
clock can be viewed as a superposition of the high frequency noise of the
local oscillator riding on the low frequency portion of the input reference
signal. In phase locked operation the high frequency noise must be bounded,
and is uncorrelated (white) for large observation periods relative to the
bandwidth of the phase locked loop.
.PP
Under ideal conditions, the only non\(hyzero parameter of the model is
the white noise PM component.
.RT
.sp 1P
.LP
A.1.2
	\fIStressed operation\fR 
.sp 9p
.RT
.PP
In the presence of interruptions, the stability of the output
timing signal behaves as a white noise FM process as the observation period 
is increased to be within the tracking bandwidth of the PLL. The presence 
of white noise FM can be justified based on the simple fact that in general, 
network 
clocks extract time interval, rather than absolute time from the time
reference. An interruption is by nature a short period during which the
reference time interval is not available. When reference is restored there 
is some ambiguity regarding the actual time difference between the local 
clock and the reference. Depending on the sophistication of the clock phase 
build\(hyout 
there can be various levels of residual phase error which occur for each
interruption. There is a random component which is independent from one
interruption event to the next which results in a random walk in phase, 
i.e.\ a white noise FM noise source. 
.PP
In addition to the white noise FM component, interruption events can actually 
result in a frequency offset between the clock and its reference. This 
frequency offset (y\db\\di\\da\\ds\u) results from a bias in the phase 
build\(hyout when reference is restored. This is a critical point. The 
implications of this effect are that in actual network environments there 
is some accumulation of 
frequency offset through a chain of clocks. Thus, clocks controlled by 
the same primary reference clock are actually operating plesiochronously 
to some 
degree.
.PP
To summarize, under stress conditions the non\(hyzero parameters of the 
clock model are the white noise FM component (e\df\\dm\u) and the frequency 
offset component (y\db\\di\\da\\ds\u). The stressed category of operation
reflects a realistic characterization of what \*Qnormal\*U operation of a clock
is.
.RT
.sp 1P
.LP
A.1.3
	\fIHoldover operation\fR 
.sp 9p
.RT
.PP
In holdover, the key components of the clock model are the
frequency drift (D) and the initial frequency offset (y\db\\di\\da\\ds\u). 
The drift term accounts for the significant ageing associated with quartz 
oscillators. The initial frequency offset is associated with the intrinsic
setability of the local oscillator frequency.
.bp
.RT
.sp 1P
.LP
A.2
	\fIRelationship of slave clock model to TIE performance\fR 
.sp 9p
.RT
.PP
It is useful to consider the relationship between the clock model and the 
Time Interval Error (TIE) that would be expected. It is proposed that the 
two sample Allan variance be used to describe the stochastic portion of 
the clock model. The following equations apply for the three categories 
of 
operation:
.RT
.LP
	\fIIdeal\fR \v'6p'
.ad r
.ad b
.RT
.LP
	\fIStressed\fR \v'6p'
.ad r
.ad b
.RT
.LP
	\fIHoldover\fR \v'6p'
.ad r
.ad b
.RT
.LP
where,
.LP
	\(*s\dT\\dI\\dE\u	is the standard deviation of the relative
time interval error of the clock output compared to
the reference over the observation time\ \fIt\fR ;
.LP
\fR 
	\(*s, (\(*t)
	is the two sample standard deviation describing the
random frequency fluctuation of the clock, and
.LP
\fR 
	\(*s\db\\di\\da\\ds\u	describes the two sample standard
deviation of the frequency bias.
.sp 1P
.LP
A.3.
	\fIGuidelines concerning the measurement of jitter and wander\fR 
.sp 9p
.RT
.PP
\fR 
Verification of compliance with jitter and wander specifications
requires standardized measurement methodologies to eliminate ambiguities 
in the measurements and in the interpretation and comparison of measurement 
results. Guidance concerning the measurement of jitter and wander is contained 
in 
Supple
ment\ No.\ 35.
.RT
.LP
.rs
.sp 24P
.LP
\fBMONTAGE:\ \fR DEBUT DE REC.\ G.821 A LA FIN DE CETTE PAGE
.sp 1P
.RT
.LP
.bp