.rs .\" Troff code generated by TPS Convert from ITU Original Files .\" Not Copyright ( c) 1991 .\" .\" Assumes tbl, eqn, MS macros, and lots of luck. .TA 1c 2c 3c 4c 5c 6c 7c 8c .ds CH .ds CF .EQ delim @@ .EN .nr LL 40.5P .nr ll 40.5P .nr HM 3P .nr FM 6P .nr PO 4P .nr PD 9p .po 4P .rs \v | 5i' .sp 2P .LP \fBRecommendation G.708\fR .RT .sp 2P .sp 1P .ce 1000 \fBNETWORK NODE INTERFACE FOR THE SYNCHRONOUS DIGITAL HIERARCHY\fR .EF '% Fascicle\ III.4\ \(em\ Rec.\ G.708'' .OF '''Fascicle\ III.4\ \(em\ Rec.\ G.708 %' .ce 0 .sp 1P .ce 1000 \fI(Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .LP The CCITT, .sp 1P .RT .sp 1P .LP \fIconsidering\fR .sp 9p .RT .PP (a) that network node interface (NNI) specifications are necessary to enable interconnection of synchronous digital network elements for transport of payloads, including digital signals of the asynchronous hierarchy defined in Recommendation G.702; .PP (b) that Recommendation G.707 describes the advantages offered by a synchronous digital hierarchy and multiplexing method and specifies a set of synchronous digital hierarchy bit rates; .PP (c) that Recommendation G.709 specifies the multiplexing structures; .PP (d) that Recommendations G.707, G.708 and G.709 form a coherent set of specifications for the synchronous digital hierarchy and NNI; .PP (e) that Recommendation G.802 specifies the interworking between networks based on different asynchronous digital hierarchies and speech encoding laws, .sp 1P .LP \fIrecommends\fR .sp 9p .RT .PP that the frame structure for multiplexed digital signals at the network node interface of a synchronous digital network including ISDN should be as described in this Recommendation. .sp 2P .LP \fB1\fR \fBLocation of NNI\fR .sp 1P .RT .PP Figure 1\(hy1/G.708 gives a possible network configuration to illustrate the location of the network node interface specified in this Recommendation. .RT .LP .rs .sp 21P .ad r \fBFigure 1\(hy1/G.708, p. \fR .sp 1P .RT .ad b .RT .LP .bp .sp 2P .LP \fB2\fR \fBBasic multiplexing principle and multiplexing elements\fR .sp 1P .RT .sp 1P .LP 2.1 \fIGeneral\fR .sp 9p .RT .PP Frame structures and overheads in this Recommendation are mainly in the context of circuit mode connection types rather than asynchronous transfer mode (ATM). ATM based multiplexing principles are under study. .PP Figure 2\(hy1/G.708 shows the relationship between various multiplexing elements that are defined below, and illustrates possible multiplexing structures. .PP Figures 2\(hy2/G.708, 2\(hy3/G.708 and 2\(hy4/G.708 are examples of how various signals are multiplexed using these multiplexing elements. .PP The legends used in these figures are defined in\ \(sc\ 2.2. .PP Details of the multiplexing method and mappings are given in Recommendation\ G.709. .PP \fINote\fR \ \(em\ When signals at bit rates of the various multiplexing elements of the synchronous digital hierarchy (Recommendations\ G.707, G.708, G.709) are different from existing hierarchy levels in Recommen dation\ G.702, the signals are not required to be transported via digital networks which are in line with Recommendation\ G.702. .RT .sp 2P .LP 2.2 \fIDefinitions\fR .sp 1P .RT .sp 1P .LP 2.2.1 \fIContainer\fR , \fIC\(hyn (n = 1 to 4)\fR .sp 9p .RT .PP This element is a defined unit of payload capacity which is dimensioned to carry any of the levels currently defined in Recommendation G.702 and may also provide capacity for transport of broadband signals which are not yet defined. .RT .sp 1P .LP 2.2.2 \fIVirtual container\fR , \fIVC\fR \fI\(hyn\fR .sp 9p .RT .PP Two types of virtual containers have been identified: .RT .LP \(em \fIBasic virtual container, VC\(hyn (n = 1, 2)\fR .LP This element comprises a single C\(hy\fIn (n = 1, 2)\fR plus the basic virtual container path overhead (POH) appropriate to that level. .LP \(em \fIHigher order virtual container to VC\(hyn (n = 3, 4)\fR .LP This element comprises a single C\(hy\fIn (n = 3, 4)\fR , an assembly of tributary unit groups (TUG\(hy2s) or an assembly of TU\(hy3s, together with virtual container POH appropriate to that level. .LP .rs .sp 17P .ad r \fBFigure 2\(hy1/G.708, p. 2\ \ \ A L'ITALIENNE\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 2\(hy2/G.708, p. 3\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 2\(hy3/G.708, p. 4\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 23P .ad r \fBFigure 2\(hy4/G.708, p. 5\fR .sp 1P .RT .ad b .RT .sp 1P .LP 2.2.3 \fITributary unit\fR \fITU\fR \fI\(hyn (n = 1 to 3)\fR .sp 9p .RT .PP This element consists of a virtual container plus a tributary unit pointer. A tributary unit pointer indicates the phase alignment of the virtual container (VC\(hy\fIn\fR ) with respect to the POH of the next higher level virtual containers in which it resides. The tributary unit pointer location is fixed with respect to this higher level POH. .PP In certain applications (for example, synchronous mapping providing direct observability of 64 kbit/s channels) the basic virtual container has a fixed phase\(hyalignment with respect to the higher level virtual container. In this case, the basic virtual container (VC\(hy1) POH and TU\(hy1 pointer are null. .RT .sp 1P .LP 2.2.4 \fITributary unit group\fR , \fITUG\fR \fI\(hy2\fR .sp 9p .RT .PP This element consists of a homogeneous assembly of TU\(hy1s or a single TU\(hy2. .RT .sp 1P .LP 2.2.5 \fIAdministrative unit, AU\fR \fI\(hyn (n = 3, 4)\fR .sp 9p .RT .PP This element consists of a VC\(hy\fIn\fR (\fIn\fR = 3, 4) plus an administrative unit pointer (AU\ PTR) . An administrative unit pointer indicates the phase alignment of the VC\(hy\fIn (n = 3, 4)\fR with respect to the STM\(hy1 frame. The administrative unit pointer location is fixed with respect to the STM\(hy1 frame. .RT .sp 1P .LP 2.2.6 \fISynchronous transport module level 1, STM\(hy1\fR .sp 9p .RT .PP This element is the basic building block of the synchronous digital hierarchy and it comprises either one AU\(hy4 or multiple AU\(hy3s, together with the section overhead (SOH). .RT .sp 1P .LP 2.2.7 \fISynchronous transport module\fR \fIlevel N, STM\(hyN\fR .sp 9p .RT .PP This element defines the N\(hyth level of the synchronous\(hydigital hierarchy and contains N synchronously multiplexed STM\(hy1 signals. .PP The STM\(hyN\(hysignal can be obtained via single\(hyor multiple\(hystage multiplexing. .PP Values of N correspond to the synchronous digital hierarchy levels given in Recommendation\ G.707. .bp .RT .LP \fB3\fR \fBFrame structure\fR .sp 1P .RT .sp 2P .LP 3.1 \fILevel 1: 155 520 kbit/s (STM\(hy1)\fR .sp 1P .RT .sp 1P .LP 3.1.1 \fIBasic frame structure\fR .sp 9p .RT .PP The STM\(hy1 frame structure is shown in Figure\ 3\(hy1/G.708. The three main areas of the STM\(hy1 frame are indicated: .RT .LP \(em section overhead; .LP \(em AU pointers; .LP \(em STM\(hy1 payload. .LP .rs .sp 16P .ad r \fBFigure 3\(hy1/G.708, p. \fR .sp 1P .RT .ad b .RT .sp 1P .LP 3.1.2 \fISection overhead\fR .sp 9p .RT .PP Rows 1\(hy3 and 5\(hy9 of columns 1\(hy9 of the STM\(hy1 in Figure 3\(hy1/G.708 are dedicated to the section overhead. .PP The allocation of section overhead capacity and functions is given in Figure 3\(hy4a/G.708. An explanation of the overhead functions is given in\ \(sc\ 5. .RT .sp 1P .LP 3.1.3 \fIAdministrative unit\fR \fI(AU) pointers\fR .sp 9p .RT .PP Row 4 of columns 1\(hy9 and row 1\(hy3 of columns 11\(hy14 in Figure 3\(hy1/G.708 are available for AU pointers. The positions of the pointers of the AUs for different organizations of the STM\(hy1 payload are shown in Table 3\(hy1/G.708. The application of pointers and their detailed specifications are given in Recommendation\ G.709. .RT .ce \fBH.T. [T1.708]\fR .ce TABLE\ 3\(hy1/G.708 .ce \fBPosition of AU pointers\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(36p) | cw(108p) . AU Position of AU pointer _ .T& cw(36p) | cw(108p) . 31 Areas A and B _ .T& cw(36p) | cw(108p) . 32 Area A\fBs and B\fR _ .T& cw(36p) | cw(108p) . \ 4 Area A\fBs and B\fR _ .TE .nr PS 9 .RT .ad r \fBTable 3\(hy1/G.708 [T1.708], p. \fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 3.1.4 \fIAdministrative units\fR \fIin the STM\(hy1\fR .sp 9p .RT .PP The STM\(hy1 payload can suppport the following types and numbers of administrative units: .RT .LP \(em one AU\(hy4; or three AU\(hy32s; or four AU\(hy31s. .PP The VC\(hy\fIn\fR associated with each AU\(hy\fIn\fR does not have a fixed phase with respect to the STM\(hy1 frame. The location of the first byte of the VC\(hy\fIn\fR is indicated by the AU\(hy\fIn\fR pointer. The AU\(hy\fIn\fR pointer is in a fixed location in the STM\(hy1 frame as illustrated in Figures\ 2\(hy2/G.708 to 2\(hy4/G.708 and 3\(hy1/G.708 to 3\(hy3/G.708. .PP The AU\(hy4 may be used to carry, via the VC\(hy4, three TU\(hy32s or four TU\(hy31s. This nested arrangement is illustrated in Figures 3\(hy2/G.708 and 3\(hy3/G.708. The VC\(hy3 associated with each TU\(hy3 does not have a fixed phase relationship with respect to the start of the VC\(hy4. The TU\(hy3 pointer is in a fixed location in the VC\(hy4 and the location of the first byte of the VC\(hy3 is indicated by the TU\(hy3 pointer (illustrated in Figures 3\(hy2/G.708 and 3\(hy3/G.708). .RT .LP .rs .sp 22P .ad r \fBFIGURE 3\(hy2/G.708,p .\fR .sp 1P .RT .ad b .RT .LP .rs .sp 17P .ad r \fBFIGURE 3\(hy3/G.708,p .\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 3.1.5 \fIVC\(hy4 and VC\(hy3 path overheads\fR .sp 9p .RT .PP The allocation of the VC\(hy4 and VC\(hy3 path overhead capacity and functions is given in Figure 3\(hy4/G.708. An explanation of the overhead functions is given in\ \(sc\ 5. .PP The position of the VC\(hy4 and VC\(hy3 path overhead is specified in Recommendation\ G.709. .RT .LP .rs .sp 26P .ad r \fBFigure 3\(hy4/G.708, p. \fR .sp 1P .RT .ad b .RT .sp 1P .LP 3.2 \fILevel 4: 622 080 kbitB/Fs (STM\(hy4)\fR .sp 9p .RT .PP This level is obtained by one\(hybyte interleaving of four STM\(hy1s as illustrated in Figure 3\(hy5/G.708. .PP The SOH of the STM\(hy1s shall be 125 s phase aligned prior to multiplexing such that the SOH of the resulting STM\(hy4 is contained in the first 36 columns. The AU pointer value(s) of each STM\(hy1 is/are adjusted to indicate the start of the VC(s) with respect to this new position of the AU pointer(s) which is fixed relative to the STM\(hy4 SOH. .RT .LP .rs .sp 10P .ad r \fBFIGURE 3\(hy5/G.708,p .\fR .sp 1P .RT .ad b .RT .LP .bp .sp 2P .LP \fB4\fR \fBInterconnection of STM\(hy1s\fR .sp 1P .RT .PP The synchronous digital hierarchy, specified in Recommendations\ G.707, G.708 and G.709, is designed to be universal, allowing transport of a large variety of signals including those specified in Recommendation\ G.702. .PP However, there are a number of options for structuring an STM\(hy1. This section provides guidelines for the interconnection of STM\(hy1s. Two general cases are considered: .RT .LP \(em Case 1: STM\(hy1s having the same structure (detailed in\ \(sc\ 4.1); .LP \(em Case 2: STM\(hy1s having different structures (detailed in\ \(sc\ 4.2). .sp 1P .LP 4.1 \fIInterconnection of STM\(hy1s having the same structure\fR .sp 9p .RT .PP The interconnection unit used between STM\(hy1s is the VC associated with the AU. This arrangement is shown in row\ i) of Table 4\(hy1/G.708. .RT .sp 1P .LP 4.2 \fIInterconnection of STM\(hy1s having different structures\fR .sp 9p .RT .PP In the case of STM\(hy1s having different structures, the following guidelines should be used to facilitate interconnection by bilateral agreement or to resolve contention. .PP The method of interconnection between STM\(hy1s having different structures depends on whether the type of AU is different or whether the type of TUG is different. The cases are considered in three categories: .RT .LP \(em different types of AU\(hy3s carrying a C\(hy3 payload; .LP \(em different types of AU carrying the same type of TUG\(hy2; .LP \(em different types of TUG\(hy2s. .sp 1P .LP 4.2.1 \fIDifferent types of AU\(hy3s carrying a C\(hy3 payload\fR .sp 9p .RT .PP For the interconnection of different types of AU\(hy3s carrying a C\(hy3 payload, the C\(hy3 payload is transferred from the AU\(hy3 to a corresponding TU\(hy3. This TU\(hy3 is then assembled into a VC\(hy4 using the nested approach illustrated in Figure\ 3\(hy3/G.708. This arrangement is shown in row\ ii) of Table 4\(hy1/G.708, and is intended to facilitate the transit of C\(hy3 in a VC\(hy3 across a network which cannot support the associated AU\(hy3. .RT .sp 1P .LP 4.2.2 \fIDifferent types of AU carrying the same type of TUG\fR .sp 9p .RT .PP For the interconnection of a different type of AU carrying the same type of TUG\(hy2, the TUG\(hy2s are transferred between the dissimilar AUs. In the absence of bilateral agreement on an AU\(hy3 type, the AU\(hy4 shall be used. This arrangement is shown in row\ iii) of Table 4\(hy1/G.708. .RT .sp 1P .LP 4.2.3 \fIDifferent types of TUG\(hy2s\fR .sp 9p .RT .PP For the interconnection of different types of TUG\(hy2s, the TU\(hy1s are transferred from the TUG\(hy22 to the TUG\(hy21. The TUG\(hy21 is used as the interconnection unit. In the absence of bilateral agreement on an AU\(hy3 type, the TUG\(hy21s are directly assembled into a VC\(hy4. This arrangement is shown in row\ iv) of Table 4\(hy1/G.708. .PP The method of interconnection between an AU\(hy31 containing TUG\(hy21s and an AU\(hy31 containing TUG\(hy22s is for further study. .RT .sp 2P .LP \fB5\fR \fBOverhead functions\fR .sp 1P .RT .sp 1P .LP 5.1 \fITypes of overhead\fR .sp 9p .RT .PP Several types of overhead have been identified for application in the synchronous digital hierarchy. The types of overhead described below and their applications are shown in Figure\ 5\(hy1/G.708. .RT .sp 1P .LP 5.1.1 \fISection overhead\fR \fI(SOH)\fR .sp 9p .RT .PP Section overhead capacity is added to either an AU\(hy4 or an assembly of AU\(hy3s to create an STM\(hy1. The content always includes STM\(hy1 framing. Content representing section performance monitoring and other maintenance and operational functions can be added or modified without disassembly of the STM\(hy1, as appropriate, for various configurations of elements (e.g. intermediate regenerator monitoring, protection switching control). .bp .RT .ce \fBH.T. [T2.708]\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(342p) . TABLE\ 4\(hy1/G.708 .T& cw(342p) . { \fBInterconnection of STM\(hy1s\fR } .TE .TS center box ; lw(12p) | cw(54p) | cw(66p) | cw(24p) sw(18p) | cw(72p) | cw(54p) | cw(42p) , ^ | ^ | ^ | c | c | ^ | ^ | ^ . STM\(hy1 structure A Conversion steps Interconnection Conversion steps STM\(hy1 structure B Parameters { STM\(hy1 structure if needed } Intercon\(hy nection unit _ .T& cw(12p) | lw(54p) | lw(66p) | lw(24p) | lw(18p) | lw(72p) | lw(54p) | lw(42p) . i) { AU\(hy\fIx\fR /C\(hy\fIx\fR or TUG\(hy2\fIp\fR } { AU\(hy\fIx\fR \(ra VC\(hy\fIx\fR } AU\(hy\fIx\fR VC\(hy\fIx\fR { VC\(hy\fIx\fR \(<- AU\(hy\fIx\fR } { AU\(hy\fIx\fR /C\(hy\fIx\fR or TUG\(hy2\fIp\fR } { \fIx\fR = 4, 32 or 31 \fIp\fR = 1 or 2 } _ .T& cw(12p) | lw(54p) | lw(66p) | lw(24p) | lw(18p) | lw(72p) | lw(54p) | lw(42p) . ii) { AU\(hy3\fIx\fR /C\(hy3\fIx\fR } { AU\(hy3\fIx\fR \(ra VC\(hy3\fIx\fR \(ra TU\(hy3\fIx\fR \(ra \(ra VC 4 } AU\(hy4 VC\(hy4 VC\(hy4 \(<- AU\(hy4 { AU\(hy4/TU\(hy3\fIx\fR /C\(hy3\fIx\fR } \fIx\fR = 1 or 2 _ .T& cw(12p) | lw(54p) | lw(66p) | lw(24p) | lw(18p) | lw(72p) | lw(54p) | lw(42p) . iii) { AU\(hy\fIx\fR /TUG\(hy2\fIp\fR } { AU\(hy\fIx\fR \(ra VC\(hy\fIx\fR \(ra TUG\(hy2\fIp\fR } { AU\(hy\fIy\fR | ua\d\u)\d } TUG\(hy2\fIp\fR { TUG\(hy2\fIp\fR \(<- VC\(hy\fIz\fR \(<- AU\(hy\fIz\fR } { AU\(hy\fIz\fR /TUG\(hy2\fIp\fR } { \fIx\fR = 4, 32 or 31 \fIy\fR = 4, 32 or 31 \fIz\fR = 4, 32 or 31; \fIz\fR \(!= \fIx\fR \fIp\fR = 1 or 2 } _ .T& cw(12p) | lw(54p) | lw(66p) | lw(24p) | lw(18p) | lw(72p) | lw(54p) | lw(42p) . iv) { AU\(hy\fIx\fR /TUG\(hy22/TU\(hy1\fIp\fR } { AU\(hy\fIx\fR \(ra VC\(hy\fIx\fR \(ra TUG\(hy21 } { AU\(hy\fIy\fR | ua\d\u)\d } TUG\(hy21 { TUG\(hy21 \(<- TU\(hy1\fIp\fR \(<- TUG\(hy22 \(<- \(<- VC\(hy\fIz\fR \(<- AU\(hy\fIz\fR } { AU\(hy\fIz\fR /TUG\(hy22/TU\(hy1\fIp\fR } { \fIx\fR = 4, 32 or 31 \fIy\fR = 4, 32 or 31 \fIz\fR = 4 or 31; \fIz\fR \(!= \fIx\fR \fIp\fR = 1 or 2 (see note) } .TE .LP/ Item to the left is carrying item to the right. .IP \(ra Conversion \*QFrom \(ra To\*U (to arrive at the interconnection unit). .LP \ua\d\u)\d In the absence of a bilateral agreement on an AU\(hy3, an AU\(hy4 should be used. .LP \fINote\fR \ \(em\ The case where \fIx\fR = 31 and \fIz\fR = 31 is for further study. .nr PS 9 .RT .ad r \fBTableau 4\(hy1/G.708 [T2.708], p. 12\ \ \ A L'ITALIENNE\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 5.1.2 \fIVirtual container path overhead\fR \fI(POH)\fR .sp 9p .RT .PP Virtual container path overhead provides for communication between the point of assembly of a virtual container and its point of disassembly. Two categories of virtual container path overhead have been identified: .RT .LP \(em \fIBasic virtual container path overhead\fR \fI(VC\(hy1, 2 POH)\fR .LP Basic virtual container POH is added to the container (C\(hy1, 2) when the VC\(hy1, 2 is created. Among the functions included in this overhead are virtual container path performance monitoring, signals for maintenance purposes and alarm status indications. .LP \(em \fIHigher order virtual container path overhead\fR \fI(VC\(hy3, 4 POH)\fR .LP VC\(hy3 POH is added to either an assembly of TUG\(hy2s or a C\(hy3 to form a VC\(hy3. VC\(hy4 POH is added to either an assembly of TU\(hy3s or a C\(hy4 to form a VC\(hy4. Among the functions included within this overhead are virtual container path performance monitoring, alarm status indications, signals for maintenance purposes and multiplex structure indications (VC\(hy3,4 composition). .LP .rs .sp 22P .ad r \fBFigure 5\(hy1/G.708, p. \fR .sp 1P .RT .ad b .RT .sp 1P .LP 5.2 \fIOverhead descriptions\fR .sp 9p .RT .PP The location of the various section and VC\(hy3, 4 path overhead bytes in the STM\(hy1 frame is illustrated in Figure 3\(hy4/G.708. .RT .sp 2P .LP 5.2.1 \fISOH byte descriptions\fR .sp 1P .RT .sp 1P .LP 5.2.1.1 \fIFraming: A1, A2\fR .sp 9p .RT .PP Six bytes are dedicated to each STM\(hy1. The pattern shall be A1A1A1A2A2A2 (A1=11110110, A2=00101000). These bytes shall be provided in all STM\(hy1 signals within an STM\(hyN. .RT .sp 1P .LP 5.2.1.2 \fIData communication channel: D1\(hyD12\fR .sp 9p .RT .PP Twelve bytes are allocated for section data communication. These bytes are defined only for STM\(hy1 No.\ 1 of an STM\(hyN signal. .bp .RT .sp 1P .LP 5.2.1.3 \fISTM identifier: C1\fR .sp 9p .RT .PP This is a unique number assigned to an STM\(hy1 prior to it being multiplexed to a higher STM\(hyN level. Upon demultiplexing, this byte may be used to identify the position of any particular STM\(hy1 within the incoming STM\(hyN signal. .RT .sp 1P .LP 5.2.1.4 \fIOrderwire\fR : \fIE1, E2\fR .sp 9p .RT .PP These two bytes provide orderwire channels for voice communication. These bytes are defined only for STM\(hy1 No.\ 1 of an STM\(hyN signal. .RT .sp 1P .LP 5.2.1.5 \fIUser channel: F1\fR .sp 9p .RT .PP This byte is reserved for user purposes (e.g. network operators). This byte is defined only for STM\(hy1 No.\ 1 of an STM\(hyN signal. .RT .sp 1P .LP 5.2.1.6 \fIBIP\(hy8: B1\fR .sp 9p .RT .PP One byte is allocated in each STM\(hy1 for a bit error monitoring function of an elementary regenerator section. This function shall be a Bit Interleaved Parity 8 (BIP\(hy8) code using even parity. The BIP\(hy8 is computed over all bits of the previous STM\(hyN frame after scrambling and is placed in byte B1 before scrambling. (For details of the scrambling process, see Recommendation G.709.) The B1 byte shall be monitored and recomputed at every regenerator. .PP \fINote\fR \ \(em\ Bit Interleaved Parity\(hyN (BIP\(hyN) code is defined as a method of error monitoring. With even parity, an N bit code is generated by the transmitting equipment over a specified portion of the signal in such a manner that the first bit of the code provides even parity over the first bit of all N\(hybit sequences in the covered portion of the signal, the second bit provides even parity over the second bit of all N\(hybit sequences within the specified portion, etc. Even parity is generated by setting the BIP\(hyN bits so that there are an even number of 1s in each of all the N\(hybit sequences including the BIP\(hyN. .RT .sp 1P .LP 5.2.1.7 \fIBIP\(hy24: B2\fR x \fI3\fR .sp 9p .RT .PP Three bytes are allocated in each STM\(hy1 for a bit error monitoring function of a section. This function shall be a Bit Interleaved Parity 24 (BIP\(hy24) code using even parity. The BIP\(hy24 is computed over all bits of the previous STM\(hy1 frame except for the first three rows of section overhead (A1 through D3) and is placed in bytes B2 before scrambling. This parity code is not recomputed at regenerators. These bytes shall be provided in all STM\(hy1 signals within an STM\(hyN signal. .RT .sp 1P .LP 5.2.1.8 \fIAPS channel: K1, K2\fR .sp 9p .RT .PP Two bytes are allocated for Automatic Protection Switching (APS) signalling. These bytes are defined only for STM\(hy1 No.\ 1 of an STM\(hyN signal. .RT .sp 1P .LP 5.2.1.9 \fISpare: Z1, Z2\fR .sp 9p .RT .PP Six bytes are allocated for functions not yet defined. These bytes have no defined value. These bytes are reserved in all STM\(hy1s of an STM\(hyN. .RT .sp 2P .LP 5.2.2 \fIAU pointer descriptions\fR .sp 1P .RT .sp 1P .LP 5.2.2.1 \fIPointer value\fR .sp 9p .RT .PP Two bytes are allocated for a pointer which indicates the offset in bytes between the pointer and the first byte of the associated virtual container POH. For a complete specification and location of these bytes, see Recommendation\ G.709. .RT .sp 1P .LP 5.2.2.2 \fIPointer action\fR .sp 9p .RT .PP Three pointer action bytes are allocated in an AU\(hy4 for frequency justification purposes. One pointer action byte is allocated for AU\(hy3s and TU\(hy\fIn\fR s. For a complete specification of these bytes, refer to Recommendation\ G.709. .PP In the event of a negative justification, they carry valid information. .bp .RT .sp 2P .LP 5.2.3 \fIVC\(hyn (n = 3, 4) POH byte descriptions\fR .sp 1P .RT .sp 1P .LP 5.2.3.1 \fIPath BIP\(hy8: B3\fR .sp 9p .RT .PP One byte is allocated in each virtual container for a path bit error monitoring function. This function shall be a BIP\(hy8 code using even parity. The BIP\(hy8 is computed over all bits of the previous container and is placed in the B3 byte. .RT .sp 1P .LP 5.2.3.2 \fIPath status: G1\fR .sp 9p .RT .PP One byte is allocated to return the VC\(hy\fIn\fR path terminating status performance information to the VC\(hy\fIn\fR path originating point. .RT .sp 1P .LP 5.2.3.3 \fISignal label: C2\fR .sp 9p .RT .PP One byte is allocated to indicate the composition of the VC\(hy\fIn\fR payload. .RT .sp 1P .LP 5.2.3.4 \fIVC\(hy\fR n \fIpath user channel: F2\fR .sp 9p .RT .PP One byte is allocated for user communication purposes. .RT .sp 1P .LP 5.2.3.5 \fIVC\(hy\fR n \fIpath trace\fR : \fIJ1\fR .sp 9p .RT .PP This byte is used at the VC\(hy\fIn\fR termination point to verify the VC\(hy\fIn\fR path connection. .RT .sp 1P .LP 5.2.3.6 \fISpare: Z3\(hyZ5\fR .sp 9p .RT .PP Three bytes are allocated for as yet undefined purposes. .RT .sp 1P .LP 5.2.3.7 \fIMultiframe indicator: H4\fR .sp 9p .RT .PP This byte is allocated to provide a multiframe indication, when required. .RT .sp 2P .LP \fB6\fR \fBPhysical specification of the NNI\fR .sp 1P .RT .PP Specification for physical, electrical or optical characteristics of the NNI will be contained in another Recommendation which is under study. \v'6p' .RT .sp 2P .LP \fBRecommendation\ G.709\fR .RT .sp 2P .sp 1P .ce 1000 \fBSYNCHRONOUS\ MULTIPLEXING\ STRUCTURE\fR .EF '% Fascicle\ III.4\ \(em\ Rec.\ G.709'' .OF '''Fascicle\ III.4\ \(em\ Rec.\ G.709 %' .ce 0 .sp 1P .ce 1000 \fR \fI(Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .LP The\ CCITT, .sp 1P .RT .sp 1P .LP \fIconsidering\fR .sp 9p .RT .PP (a) that Recommendation\ G.707 describes the advantages offered by a synchronous digital hierarchy and multiplexing method and specifies a set of synchronous digital hierarchy bit rates; .PP (b) that Recommendation\ G.708 specifies .LP \(em the general principles and frame structure of the network node interface (NNI) for the synchronous digital hierarchy; .LP \(em the overall frame size of 9 rows \(mu 270 columns and section overhead (SOH) definition and its byte allocation; .LP \(em arrangements for international synchronous interconnection of STM\(hy1s; .PP (c) that Recommendations\ G.707, G.708 and G.709 form a coherent set of specifications for the synchronous digital hierarchy and NNI, .bp .sp 1P .LP \fIrecommends\fR .sp 9p .RT .PP that the formats for mapping multiplexing elements into the STM\(hy1 at the Network Node Interface (NNI) and the method of multiplexing to STM\(hyN shall be as described in this Recommendation. .sp 2P .LP \fB1\fR \fBBasic multiplexing structure\fR .sp 1P .RT .PP Descriptions of the various multiplexing elements are given in Recommendation G.708. .PP The relationships between the various multiplexing elements are shown in Figure\ 1\(hy1/G.709. The detailed multiplexing structure is described in the following sections. .RT .LP .rs .sp 24P .ad r \fBFigure 1\(hy1/G.709, p.\fR .sp 1P .RT .ad b .RT .LP \fB2\fR \fBMapping formats and multiplexing method\fR .sp 1P .RT .sp 2P .LP 2.1 \fIMapping and multiplexing up to STM\(hy1\fR .sp 1P .RT .sp 1P .LP 2.1.1 \fIMapping of VC\(hy4 into AU\(hy4\fR .sp 9p .RT .PP The STM\(hy1 mapping format for transporting one VC\(hy4 in an AU\(hy4 is shown in Figure\ 2\(hy1/G.709. The VC\(hy4 consists of a 9\(hyrow by 261\(hycolumn payload structure; the first column of the VC\(hy4 is devoted to path overhead (POH). The payload of the VC\(hy4 shown in Figure\ 2\(hy1/G.709 is a single C\(hy4. Other possible VC\(hy4 payloads include a single 139 | 64\ kbit/s signal in a C\(hy4, four VC\(hy31s (shown in Figure\ 2\(hy2/G.709 and carried in four TU\(hy31s), three VC\(hy32s (shown in Figure\ 2\(hy3/G.709 and carried in three TU\(hy32s), and a group of either 21 TUG\(hy21s or 16 TUG\(hy22s (shown in Figure\ 2\(hy4/G.709). .PP The STM\(hy1 format shown in Figure 2\(hy1/G.709 consists of an AU\(hy4 plus section overhead (SOH). The VC\(hy4 does not have a fixed phase with respect to the AU\(hy4 (and the STM\(hy1); therefore, the location of the first byte of the VC\(hy4 with respect to the AU\(hy4 frame is given by the AU\(hy4 pointer. Note that the AU\(hy4, including the AU\(hy4 pointer, has a fixed location in the STM\(hy1 frame. .bp .RT .LP .rs .sp 24P .ad r \fBFigure 2\(hy1/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 2.1.2 \fIMapping of four VC\(hy31s into AU\(hy4\fR .sp 9p .RT .PP The STM\(hy1 mapping format for transporting four VC\(hy31s in an AU\(hy4 is shown in Figure\ 2\(hy2/G.709. Each TU\(hy31 consists of a 9\(hyrow by 64\(hycolumn payload structure plus six bytes of POH plus a three\(hybyte TU\(hy31 pointer. The payload of the VC\(hy31 shown in Figure\ 2\(hy22/G.709 is a single C\(hy31. Other possible VC\(hy31 payloads include a single 34 | 68\ kbit/s signal in a C\(hy31 (shown in Figure\ 5\(hy10/G.709) or a group of either five TUG\(hy21s or four TUG\(hy22s (shown in Figure\ 2\(hy5/G.709). .PP The four VC\(hy31s are carried independently in the 261\(hycolumn VC\(hy4. Each of the VC\(hy31s does not have a fixed phase with respect to the start of the VC\(hy4. Therefore, the location of the first byte of each VC\(hy31 with respect to the VC\(hy4 POH is given by a 3\(hybyte TU\(hy31 pointer (H1, H2, H3). These four TU\(hy31 pointers reside in a fixed location in the VC\(hy4 as shown in Figure\ 2\(hy2/G.709. .PP As described in \(sc 2.1.1, the phase of the VC\(hy4 with respect to the AU\(hy4 is given by the AU\(hy4 pointer. .RT .sp 1P .LP 2.1.3 \fIMapping of three VC\(hy32s into AU\(hy4\fR .sp 9p .RT .PP The STM\(hy1 mapping format for transporting three VC\(hy32s in an AU\(hy4 is shown in Figure\ 2\(hy3/G.709. Each TU\(hy32 consists of a 9\(hyrow by 84\(hycolumn payload structure plus one column of POH and one 3\(hybyte TU\(hy32 pointer. The payload of the VC\(hy32 shown in Figure\ 2\(hy3/G.709 is a single C\(hy32. Other possible VC\(hy32 payloads include a single 44 | 36\ kbitB/Fs signal in a C\(hy32 or a group of seven TUG\(hy21s (shown in Figure\ 2\(hy5/G.709). .PP The three VC\(hy32s are carried independently in the 261\(hycolumn VC\(hy4. Each of the VC\(hy32s does not have a fixed phase with respect to the start of the VC\(hy4. Therefore, the location of the first byte of each VC\(hy32 with respect to the VC\(hy4 POH is given by a 3\(hybyte TU\(hy32 pointer (H1, H2, H3). These three TU\(hy32 pointers reside in a fixed location in the VC\(hy4 as shown in Figure\ 2\(hy3/G.709; 36 fixed stuff bytes are also required in the VC\(hy4. .PP As described in \(sc\ 2.1.1, the phase of the VC\(hy4 with respect to the AU\(hy4 is given by the AU\(hy4 pointer. .bp .RT .LP .rs .sp 24P .ad r \fBFigure 2\(hy2/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .rs .sp 25P .ad r \fBFigure 2\(hy3/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 2.1.4 \fIMapping of TUG\(hy2s into AU\(hy4\fR .sp 9p .RT .PP The STM\(hy1 mapping format transporting TUG\(hy21s and TUG\(hy22s into an AU\(hy4 is shown in Figure\ 2\(hy4/G.709. The AU\(hy4 can carry a group of either 21 TUG\(hy21s or 16 TUG\(hy22s. .PP The TUG\(hy21 payload structure has 9 rows and 12 columns. When used to transport TUG\(hy21s, the VC\(hy4 consists of one column of VC\(hy4 POH, eight columns of fixed stuff, and a remaining 252\(hycolumn payload structure. The 21 TUG\(hy21s are mapped into this 9\(hyrow by 252\(hycolumn structure using a fixed phase with respect to the VC\(hy4. The TUG\(hy21s are single byte interleaved as shown in Figure\ 2\(hy4/G.709. .PP The TUG\(hy22 payload structure has 9 rows and 16 columns. The VC\(hy4 consists of one column of VC\(hy4 POH, four columns of fixed stuff and 256\ payload columns when used to carry the 16 TUG\(hy22s. The TUG\(hy22s are single byte interleaved into the 9\(hyrow by 256\(hycolumn structure. .PP As described in \(sc\ 2.1.1, the phase of the VC\(hy4 with respect to the AU\(hy4 is given by the AU\(hy4 pointer. .RT .LP .rs .sp 31P .ad r \fBFigure 2\(hy4/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 2.1.5 \fIMapping of four AU\(hy31s into STM\(hy1\fR .sp 9p .RT .PP The STM\(hy1 mapping format for transporting four VC\(hy31s within four AU\(hy31s is shown in Figure\ 2\(hy6/G.709. A VC\(hy31 is defined to be a 9\(hyrow by 64\(hycolumn payload structure, plus six bytes of POH, located in row 1 to 6 of the first column, according to the figure. .PP Each AU\(hy31 pointer has a fixed phase with respect to the STM\(hy1 frame. As shown in Figure\ 2\(hy6/G.709, the four AU\(hy31 pointers are located in columns 11 to 14, rows\ 1 to 3 of the STM\(hy1, one pointer in each column. Columns 11 to 270 of the STM\(hy1 are divided between each of the AU\(hy31s; thus, each AU\(hy31 occupies alternately every fourth column. .bp .PP The phase of each VC\(hy31 is not fixed with respect to its AU\(hy31. Therefore, the location of the first byte of each VC\(hy31 with respect to the AU\(hy31 frame is given by AU\(hy31 pointer (H1, H2, H3). The payload of the VC\(hy31 shown in Figure\ 2\(hy6/G.709 is a single C\(hy31. Other possible VC\(hy31 payloads include a single 34 368\ kbit/s signal in a C\(hy31 and a group of five TUG\(hy21s or four TUG\(hy22s (shown in Figure\ 2\(hy5/G.709). .RT .LP .rs .sp 24P .ad r \fBFigure 2\(hy5/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .rs .sp 22P .ad r \fBFigure 2\(hy6/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 2.1.6 \fIMapping of three AU\(hy32s into STM\(hy1\fR .sp 9p .RT .PP The STM\(hy1 mapping format for transporting three VC\(hy32s within three AU\(hy32s is shown in Figure\ 2\(hy7/G.709. A VC\(hy32 is defined to be a 9\(hyrow by 85\(hycolumn payload structure, with the first column consisting of VC\(hy32 POH. When mapped into its AU\(hy32, two columns of fixed stuff are added to each VC\(hy32 payload to make it equal the AU\(hy32 payload capacity. These two fixed stuff columns are fixed with respect to the VC\(hy32 POH and are inserted between columns 29 and 30, and between columns 57 and 58 of the VC\(hy32. .PP Each AU\(hy32 pointer has a fixed phase with respect to the STM\(hy1 frame. As shown in Figure\ 2\(hy7/G.709, the three AU\(hy32 pointers are located in the fourth row of the first nine columns of the STM\(hy1 frame, between the bytes of the SOH. The remaining 261 columns of the STM\(hy1 are divided between each of the AU\(hy32s; thus, each AU\(hy32 occupies alternately every third column of the 261. AU\(hy32 number one consists of three bytes of AU\(hy32 pointer, plus STM\(hy1 columns 10, 13, 16, | | | where columns 1 through 9 contain the SOH and the AU\(hy32 pointers. .PP The phase of each VC\(hy32 (plus fixed stuff columns) is not fixed with respect to its AU\(hy32. Therefore, the locations of the first byte of each VC\(hy32 with respect to the AU\(hy32 frame is given by the AU\(hy32 pointer (H1, H2, H3). The payload of the VC\(hy32 shown in Figure\ 2\(hy7/G.709 is a single C\(hy32. Other possible VC\(hy32 payloads include a single 44 | 36\ kbitB/Fs signal into a C\(hy32 (shown in Figure\ 5\(hy8/G.709) and a group of seven TUG\(hy21s (shown in Figure\ 2\(hy5/G.709). .RT .LP .rs .sp 25P .ad r \fBFigure 2\(hy7/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 2.1.7 \fIMapping of TUGs into a VC\fR .sp 9p .RT .PP Figure 2\(hy5/G.709 shows the schematic mapping of TUG\(hy2s into a VC\(hy3. The details of these mappings are given in \(sc\ 5; this section presents the general multiplexing principles involved. .PP The VC\(hy31 consists of six bytes of VC\(hy31 POH plus a 9\(hyrow by 64\(hycolumn payload structure. This payload structure can be used to carry five TUG\(hy21s or four TUG\(hy22s. The individual TUG\(hy2 has a fixed location in the VC\(hy31 frame; this is shown schematically in Figure\ 2\(hy5/G.709. .PP The VC\(hy32 consists of nine bytes of VC\(hy32 POH plus a 9\(hyrow by 84\(hycolumn payload structure. This payload structure can be used to carry seven TUG\(hy21s. Again, the individual TUG\(hy21 has a fixed location in the VC\(hy32 frame. .bp .PP Each TUG\(hy21 can carry a single VC\(hy21 or four VC\(hy11s or three VC\(hy12s. Each TUG\(hy22 can carry a single VC\(hy22 or four VC\(hy12s or five VC\(hy11s. The VCs do not have a fixed phase with respect to the VC\(hy3 POH; TU pointers are used to indicate the position of the VCs in the TUG frame. .RT .sp 2P .LP 2.2 \fISTM\(hyN multiplexing\fR .sp 1P .RT .sp 1P .LP 2.2.1 \fISTM\(hyN frame format\fR .sp 9p .RT .PP The STM\(hyN signal is formed by single byte interleaving N STM\(hy1 signals. The STM\(hyN frame structure is depicted in Figure\ 2\(hy8/G.709. .PP The first byte of the STM\(hyN signal shall be the first A1 framing byte from STM\(hy1\ No.\ 1 followed sequentially by the first A1 byte from STM\(hy1\ No.\ 2 through No.\ N. The first bit to be transmitted shall be the most significant bit of the first A1 framing byte from STM\(hy1\ No.\ 1. .PP Before byte interleaving STM\(hy1 signals to form an STM\(hyN signal, all of the SOH and the AU\(hy\fIn\fR (\fIn\fR \ =\ 3 or 4) pointers in the signals to be interleaved must be 125 \(*ms\ frame aligned. The alignment is accomplished by adjusting the values of the AU\(hy\fIn\fR pointers to reflect the new relative positions of the VC\(hy\fIn\fR s. .PP Note that is is permitted to mix STM\(hy1s containing AU\(hy3s and STM\(hy1s containing AU\(hy4s in the same STM\(hyN. .RT .LP .rs .sp 22P .ad r \fBFigure 2\(hy8/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 2.2.2 \fISTM\(hyN interleaving\fR .sp 9p .RT .PP If an STM\(hyN level signal is input to a byte interleaver with STM\(hyM level output (M\ >\ N), N bytes of each STM\(hyN are consecutively placed on the output STM\(hyM signal. This method of interleaving is illustrated in Figure\ 2\(hy9/G.709 where STM\(hyX, STM\(hyY and STM\(hyZ (X\ +\ Y\ +\ Z\ =\ M) inputs are sequentially interleaved to form an STM\(hyM output. .bp .RT .LP .rs .sp 15P .ad r \fBFigure 2\(hy9/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 2.2.3 \fIConcatenated STM\(hy1s\fR .sp 9p .RT .PP STM\(hy1 signals can be concatenated together to form an STM\(hyNc which can transport payloads requiring greater than one C\(hy4 capacity. A concatenation indication, used to show that this multi\(hyC\(hy4 payload carried in a single VC\(hy4\(hyNc should be kept together, is contained in the AU\(hy4 pointer. See \(sc\ 3.4 for details. .RT .sp 2P .LP 2.3 \fIMaintenance signals\fR .sp 1P .RT .sp 1P .LP 2.3.1 \fISection maintenance signals\fR .sp 9p .RT .PP The section alarm indication signal (AIS) is detected as an all 1s in bits\ 6, 7, 8 of byte\ K2 after descrambling. .PP Far end receive failure (FERF) is to return an indication to the transmitting STM\(hyN MUX that the receiving STM\(hyN MUX has detected an incoming section failure or is receiving section AIS. .PP FERF is detected by a 110 code in bit positions 6, 7 and 8 of the K2\ APS byte after descrambling. .RT .sp 1P .LP 2.3.2 \fIPath maintenance signals\fR .sp 9p .RT .PP The VC\(hy\fIn\fR (\fIn\fR = 3, 4) unequipped indication is an all 0s VC\(hy\fIn\fR path signal label after descrambling. This code indicates to VC\(hy\fIn\fR terminating equipment that the VC\(hyn is intentionally unoccupied so that alarms can be inhibited. This code is generated as an all 0s VC\(hy\fIn\fR path signal label and a valid VC\(hyn path BIP\(hy8 (byte\ B3); the VC\(hy\fIn\fR payload is unspecified. .PP An alarm indication signal (AIS) is a signal sent downstream as an indication that an upstream failure has been detected and an alarm generated. The TU\(hy\fIn\fR (\fIn\fR \ =\ 1, 2, 3) path AIS is specified as all 1s in the entire TU\(hy\fIn\fR , including the TU\(hy\fIn\fR pointer. Similarly, the AU\(hy\fIn\fR (\fIn\fR \ =\ 3, 4) path AIS is specified as all 1s in the entire AU\(hy\fIn\fR , including the AU\(hy\fIn\fR pointer. All path AISs are carried within STM\(hyN signals having valid SOH. .PP The path status byte (G1) is used to convey the terminating path status and performance to the originator of a VC\(hy\fIn\fR (\fIn\fR \ =\ 3 or 4). Bits\ 1 through 4 convey the count of errors detected using the path BIP\(hy8 code. This code has nine legal values, 0\(hy8. The remaining seven possible values should be interpreted as zero errors. .bp .RT .sp 1P .LP 2.4 \fITiming recovery\fR .sp 9p .RT .PP The STM\(hyN (N \(>=" 1) signal must have sufficient bit timing content at the NNI. A suitable bit pattern, which prevents a long sequence of 1s and 0s, is provided by using a scrambler. Its operation shall be functionally identical to that of a frame synchronous scrambler of sequence length 127 operating at the line rate. .PP The generating polynomial shall be 1 + \fIx\fR \u6\d + \fIx\fR \u7\d. Figure\ 2\(hy10/G.709 gives a functional diagram of the frame synchronous scrambler. .PP The scrambler shall be reset to 1111111 on the most significant bit of the byte following the last byte of the first row of the STM\(hyN SOH. (This is the most significant bit of the 9\ \(mu\ N\ +\ 1 transmitted byte of the STM\(hyN; see Figure\ 2\(hy8/G.709.) This bit, and all subsequent bits to be scrambled, shall be added modulo\ 2 to the output from the \fIx\fR \u7\d position of the scrambler. The scrambler shall run continuously throughout the complete STM\(hyN frame. .PP The first row of the STM\(hyN SOH (9 \(mu N bytes, including the A1 and A2 framing bytes) shall not be scrambled. .PP \fINote\fR \ \(em\ Care should be taken in selecting the binary content of the bytes reserved for national use and which are excluded from the scrambling process of the STM\(hyN signal, to ensure that long sequences of 1s or 0s do not occur. .RT .LP .rs .sp 12P .ad r \fBFigure 2\(hy10/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 2.5 \fIConceptual steps for STM\(hyN assembly\fR .sp 9p .RT .PP For a better understanding of the detailed structure of the STM\(hyN frame shown in Figure\ 2\(hy8/G.709, the conceptual steps required to assemble the STM\(hyN frames in the direct (non\(hynested) arrangement are listed: .RT .LP 1) Each VC\(hy\fIn\fR (\fIn\fR = 3 or 4) has either six or nine bytes devoted to path overhead (POH) functions. Of these, the BIP\(hy8 error check byte (B3) is calculated over the entire contents of the VC\(hy\fIn\fR and the result is placed in the B3\ byte of the following frame. .LP If it is appropriate, the VC\(hy\fIn\fR unequipped signal consisting of an all 0s pattern for the VC\(hy\fIn\fR is inserted. (See \(sc\ 2.3.) .LP 2) After all of the required VC\(hy\fIn\fR s have been assembled, AU\(hy\fIn\fR pointer values are calculated so as to frame align all of the AU\(hy\fIn\fR s within a single STM\(hyN frame. .LP If the contents of the VC\(hy\fIn\fR are lost due to an equipment or other failure, the AU\(hy\fIn\fR path AIS signal is inserted into the AU\(hy\fIn\fR . The AU\(hy\fIn\fR path AIS is defined in \(sc\ 2.3. .LP 3) The SOH bytes are then added to the STM\(hyN frame. It is convenient to consider the last five rows of the SOH first. Of the N\ \(mu\ 45 such SOH bytes, N\ \(mu\ 9 are allocated to the N\ \(mu\ 3\ B2, N\ \(mu\ 3\ Z1 and N\ \(mu\ 3\ Z2\ bytes. Thus, each STM\(hy1 has a full complement\ (3) of these bytes in the STM\(hyN. The remaining STM\(hyN SOH bytes in the last five rows (K1 and K2, D4\(hyD12 and E2) are limited to the first STM\(hy1 in any STM\(hyN signal. The content of the unused SOH bytes of STM\(hy1\ No.\ 2 through No.\ N are for national use. .LP 4) The N \(mu 3 B2 bytes of an STM\(hyN contain a bit interleaved parity N\ \(mu\ 24 (BIP\(hyN\ \(mu\ 24) code using even parity which is calculated across the entire previous STM\(hyN frame excluding the first three rows of SOH. .LP 5) A line signal failure would result in the insertion of a section\ AIS at this point in the assembly of an STM\(hyN (see \(sc\ 2.3). .bp .LP 6) The remaining bytes of SOH contained in the first three rows (27\ \(mu\ N\ bytes) of the STM\(hyN are added next. Of these, the B1, E1, F1, D1\(hyD3 bytes are present only in STM\(hy1\ No.\ 1 of any STM\(hyN signal. The content of the unused SOH bytes of STM\(hy1\ No.\ 2 through No.\ N are for national use. .LP 7) The STM\(hy1s are then byte interleaved to form an STM\(hyN, as described in \(sc\ 2.2.2, and subsequently serialized and scrambled as described in \(sc\ 2.4. .LP 8) The final operation is the calculation of a BIP\(hy8 code over the entire STM\(hyN bit stream on a frame\(hyby\(hyframe basis. The result is loaded into byte B1 of STM\(hy1\ No.\ 1 in the following frame when the SOH is loaded. .sp 2P .LP \fB3\fR \fBPointer\fR .sp 1P .RT .sp 1P .LP 3.1 \fIAU pointer\fR .sp 9p .RT .PP The AU pointer provides a method of allowing flexible and dynamic alignment of the VC within the AU frame. .PP Dynamic alignment means that the VC is allowed to \*Qfloat\*U within the AU frame. Thus the pointer is able to accommodate differences not only in the phases of the VC and SOH, but in the frame rates as well. .RT .sp 1P .LP 3.1.1 \fIAU pointer location\fR .sp 9p .RT .PP The AU\(hy4 pointer is contained in bytes H1, H2 and H3 as shown in Figure\ 3\(hy1/G.709. The three individual AU\(hy32 pointers are contained in three separate H1, H2 and H3 bytes as shown in Figure\ 3\(hy2/G.709. Likewise the four individual AU\(hy31 pointers are contained in four separate H1, H2 and H3 bytes as shown in Figure\ 3\(hy3/G.709. .RT .LP .rs .sp 29P .ad r \fBFigure 3\(hy1/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 26P .ad r \fBFigure 3\(hy2/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .rs .sp 24P .ad r \fBFigure 3\(hy3/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 3.1.2 \fIAU pointer value\fR .sp 9p .RT .PP The pointer contained in H1 and H2 designates the location of the bytes where the VC begins. The two bytes allocated to the pointer function can be viewed as one word as shown in Figure\ 3\(hy4/G.709. The last 10\ bits (bits\ 7\(hy16) of the pointer word carry the pointer value. The two S\ bits (bits\ 5 and 6) indicate the AU type. .PP As illustrated in Figure 3\(hy4/G.709, the AU\(hy4 pointer value is a binary number with a range of 0 to 782 which indicates the offset between the pointer and the first byte of the VC. As shown in Figure 3\(hy1/G.709, the H1 and H2\ bytes contain the pointer value while the position which the pointer indicates is the very first byte of the consecutive three bytes. Figure\ 3\(hy4/G.709 also indicates two additional valid pointers: the concatenation indication (CI) and the null pointer indication (NPI). The CI is indicated by 1001 in bits\ 1\(hy4, with bits 5\(hy6 unspecified, and ten 1s in bits\ 7\(hy16. The NPI is indicated by 1001 in bits\ 1\(hy4, with bits 5\(hy6 unspecified, and five 1s in bits\ 7\(hy11 followed by five 0s in bits\ 12\(hy16. .PP As illustrated in Figure 3\(hy4/G.709, the AU\(hy32 pointer value is also a binary number with a range of 0 to 782. Since there are three AU\(hy32s in the STM\(hy1, each AU\(hy32 has its own associated H1, H2 and H3 bytes. In Figure\ 3\(hy2/G.709, the H\ bytes are shown in sequence. The first H1, H2, H3 set refers to the first AU\(hy32, and the second set to the second AU\(hy32, and so on. The same is true for the information bytes. For the AU\(hy32s, each pointer operates independently. .PP Likewise, as illustrated in Figure 3\(hy4/G.709, the AU\(hy31 pointer value is a binary number with a range of 0 to 581. Since there are four AU\(hy31s in the STM\(hy1, each AU\(hy31 has its own associated H1, H2 and H3 bytes. In Figure\ 3\(hy3/G.709, the H\ bytes are shown in sequence. The first H1, H2, H3 set refers to the first AU\(hy31, the second set to the second AU\(hy31, and so on. The same is true for the information bytes. For the AU\(hy31s, each pointer operates independently. .PP In all cases, the STM\(hy1 SOH and AU pointer bytes are not counted in the offset. For example, in an AU\(hy4, the pointer value of 0 indicates that the VC starts in the byte location that immediately follows the last H3 byte, whereas an offset of 87 indicates that the VC starts three bytes after the K2 byte. .RT .LP .rs .sp 7P .ad r \fBFigure 3\(hy4/G.709, p. 28\fR .sp 1P .RT .ad b .RT .LP .rs .sp 16P .ad r \fBFigure 3\(hy4/G.709 [T2.709], p. 28\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 3.1.3 \fIFrequency justification\fR .sp 9p .RT .PP If there is a frequency offset between the frame rate of the SOH and that of the VC, then the pointer value will be incremented or decremented as needed, accompanied by a corresponding positive or negative justification byte or bytes. Consecutive pointer operations must be separated by at least three frames (i.e.\ every fourth frame) in which the pointer value remains constant. .PP If the frame rate of the VC is too slow with respect to that of the SOH, then the alignment of the VC must periodically slip back in time and the pointer value must be incremented by one. This operation is indicated by inverting bits\ 7, 9, 11, 13 and 15 ( I\(hybits ) of the pointer word to allow 5\(hybit majority voting at the receiver. Three positive justification bytes appear immediately after the last H3 byte in the AU\(hy4 frame containing inverted I\(hybits. Subsequent pointers will contain the new offset. This is illustrated in Figure\ 3\(hy5/G.709. .PP For AU\(hy32 frames, a positive justification byte appears immediately after the associated H3 byte of the individual AU\(hy32 frame containing inverted I\(hybits. Subsequent pointers will contain the new offset. This is illustrated in Figure\ 3\(hy6/G.709. The same is true for AU\(hy31 as shown in Figure\ 3\(hy7/G.709. .PP If the frame rate of the VC is too fast with respect to that of the SOH, then the alignment of the VC must periodically be advanced in time and the pointer value must be decremented by one. This operation is indicated by inverting bits\ 8, 10, 12, 14 and 16 ( D\(hybits ) of the pointer word to allow 5\(hybit majority voting at the receiver. Three negative justification bytes appear in the H3 bytes in the AU\(hy4 frame containing inverted D\(hybits. Subsequent pointers will contain the new offset. This is illustrated in Figure\ 3\(hy8/G.709. .PP For AU\(hy32 frames, a negative justification byte appears in the H3 byte of the individual AU\(hy32 frame containing inverted D\(hybits. Subsequent pointers will contain the new offset. This is illustrated in Figure\ 3\(hy9/G.709. The same is true for AU\(hy31 as shown in Figure\ 3\(hy10/G.709. .RT .LP .rs .sp 30P .ad r \fBFigure 3\(hy5/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 3\(hy6/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 3\(hy7/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 3\(hy8/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 3\(hy9/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 3\(hy10/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 3.1.4 \fINew data flag\fR .sp 9p .RT .PP Bits 1\(hy4 (N\(hybits) of the pointer word carry a new data flag (NDF) which allows an arbitrary change of the pointer value if that change is due to a change in the payload. .PP Four bits are allocated to the flag to allow error correction. The decoding may be performed by accepting NDF enabled if at least three bits match. Normal operation is indicated by a 0110 code in the N\(hybits. NDF is indicated by inversion of the N\(hybits to 1001. The new alignment is indicated by the pointer value accompanying the NDF and takes effect at the offset indicated. NDF should be enabled when the pointer value transits between its normal value and the CI or NPI. .RT .sp 1P .LP 3.1.5 \fIPointer generation\fR .sp 9p .RT .PP The following summarizes the rules for generating the AU pointers. .RT .LP 1) During normal operation, the pointer locates the start of the VC within the AU frame. The NDF is set to 0110. .LP 2) The pointer value can only be changed by rules\ 3, 4 or 5. .LP 3) If a positive justification is required, the current pointer value is sent with the I\(hybits inverted and the subsequent positive justification opportunity is filled with dummy information. Subsequent pointers contain the previous pointer value incremented by one. No subsequent increment or decrement operation is allowed for at least three frames following this operation. .LP 4) If a negative justification is required, the current pointer value is sent with the D\(hybits inverted and the subsequent negative justification opportunity is overwritten with actual data. Subsequent pointers contain the previous pointer value decremented by one. No subsequent increment or decrement operation is allowed for at least three frames following this operation. .LP 5) If the alignment of the VC changes for any reason other than rules\ 3 or 4, the new pointer value shall be sent accompanied by NDF set to 1001. The NDF only appears in the first frame that contains the new values. The new location of the VC begins at the first occurrence of the offset indicated by the new pointer. No subsequent increment or decrement operation is allowed for at least three frames following this operation. .sp 1P .LP 3.1.6 \fIPointer interpretation\fR .sp 9p .RT .PP The following summarizes the rules for interpreting the AU pointers. .RT .LP 1) During normal operation, the pointer locates the start of the VC within the AU frame. .LP 2) Any variation from the current pointer value is ignored unless a consistent new value is received three times consecutively or it is preceded by one of rules\ 3, 4 or 5. .LP 3) If the majority of the I\(hybits of the pointer word are inverted, a positive justification operation is indicated. Subsequent pointer values shall be incremented by one. .LP 4) If the majority of the D\(hybits of the pointer word are inverted, a negative justification operation is indicated. Subsequent pointer values shall be decremented by one. .LP 5) If the NDF is set to 1001, then the coincident pointer value shall replace the current one at the offset indicated by the new pointer value regardless of the state of the receiver. .sp 1P .LP 3.2 \fITU\(hy3 pointers\fR .sp 9p .RT .PP There are two types of TU\(hy3 pointers: TU\(hy31 and TU\(hy32. The TU\(hy3 pointer provides a method of allowing flexible and dynamic alignment of VC\(hy3 within the TU\(hy3 frame, independent of the actual contents of the VC. Dynamic alignment means that the VC\(hy3 is allowed to \*Qfloat\*U within the TU\(hy3 frame. .RT .sp 1P .LP 3.2.1 \fITU\(hy3 pointer location\fR .sp 9p .RT .PP Three individual TU\(hy32 pointers are contained in the three separate H1, H2 and H3 bytes as shown in Figure\ 3\(hy11/G.709. Four individual TU\(hy31 pointers are contained in the four separate H1, H2 and H3 bytes as shown in Figure\ 3\(hy12/G.709. .bp .RT .sp 1P .LP 3.2.2 \fITU\(hy3 pointer value\fR .sp 9p .RT .PP The TU\(hy3 pointer value contained in H1 and H2 designates the location of the byte where the VC\(hy3 begins. The two bytes allocated to the pointer function can be viewed as one word as shown in Figure\ 3\(hy4/G.709. The last ten bits (bits\ 7\(hy16) of the pointer word carry the pointer value. The two S bits (bits\ 5 and 6) indicate the TU type. .PP The TU\(hy32 pointer value is a binary number with a range of 0\(hy764 which indicates the offset between the pointer and the first byte of the VC\(hy32 as shown in Figure\ 3\(hy11/G.709. .PP The TU\(hy31 pointer value is a binary number with a range of 0\(hy581 which indicates the offset between the pointer and the first byte of the VC\(hy31 as shown in Figure\ 3\(hy12/G.709. .RT .LP .rs .sp 21P .ad r \fBFigure 3\(hy11/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .rs .sp 21P .ad r \fBFigure 3\(hy12/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 3.2.3 \fIFrequency justification\fR .sp 9p .RT .PP If there is a frequency offset between the TU\(hy3 frame rate and that of the VC\(hy3, then the pointer value will be incremented or decremented as needed accompanied by a corresponding positive or negative justification byte. Consecutive pointer operations must be separated by at least three frames in which the pointer value remains constant. .PP If the frame rate of the VC\(hy3 is too slow with respect to that of the TU\(hy3 frame rate, then the alignment of the VC must periodically slip back in time and the pointer must be incremented by one. This operation is indicated by inverting bits\ 7, 9, 11, 13 and 15 (I\(hybits) of the pointer word to allow 5\(hybit majority voting at the receiver. A positive justification byte appears immediately after the individual H3 byte in the TU\(hy3 frame containing inverted I\(hybits. Subsequent TU\(hy3 pointers will contain the new offset. .PP If the frame rate of the VC\(hy3 is too fast with respect to that of the TU\(hy3 frame rate, then the alignment of the VC must be periodically advanced in time and the pointer must be decremented by one. This operation is indicated by inverting bits\ 8, 10, 12, 14 and 16 (D\(hybits) of the pointer word to allow 5\(hybit majority voting at the receiver. A negative justification byte appears in the individual H3 byte in the TU\(hy3 frame containing inverted D\(hybits. Subsequent TU\(hy3 pointers will contain the new offset. .RT .sp 1P .LP 3.2.4 \fINew data flag\fR .sp 9p .RT .PP Bits 1\(hy4 (N\(hybits) of the pointer word carry a NDF which allows an arbitrary change of the value of the pointer if that change is due to a change in the VC\(hy3. .PP Four bits are allocated to the flag to allow for error correction. The decoding may be performed by accepting NDF enabled if at least three bits match. Normal operation is indicted by a 0110 code in the N\(hybits; NDF is indicated by inversion of the N\(hybits to 1001. The new alignment is indicated by the pointer value accompanying the NDF and takes effect at the offset indicated. .RT .sp 1P .LP 3.2.5 \fIPointer generation\fR .sp 9p .RT .PP The following summarizes the rules for generating the TU\(hy3 pointers. .RT .LP 1) During normal operation, the pointer locates the start of the VC\(hy3 within the TU\(hy3 frame. The NDF is set to 0110. .LP 2) The pointer value can only be changed by rules\ 3, 4 or 5. .LP 3) If a positive justification is required, the current pointer value is sent with the I\(hybits inverted and the subsequent positive justification opportunity is filled with dummy information. Subsequent pointers contain the previous pointer value incremented by one. No subsequent increment or decrement operation is allowed for at least three frames following this operation. .LP 4) If a negative justification is required, the current pointer value is sent with the D\(hybits inverted and the subsequent negative justification opportunity is overwritten with actual data. Subsequent pointers contain the previous pointer value decremented by one. No subsequent increment or decrement operation is allowed for at least three frames following this operation. .LP 5) If the alignment of the VC changes for any reason other than rules\ 3 or 4, the new pointer value shall be sent accompanied by the NDF set to 1001. The NDF only appears in the first frame that contains the new value. The new VC location begins at the first occurrence of the offset indicated by the new pointer. No subsequent increment or decrement operation is allowed for at least three frames following this operation. .sp 1P .LP 3.2.6 \fIPointer interpretation\fR .sp 9p .RT .PP The following summarizes the rules for interpreting the TU\(hy3 pointers. .RT .LP 1) During normal operation the pointer locates the start of the VC\(hy3 within the TU\(hy3 frame. .LP 2) Any variation from the current pointer value is ignored unless a consistent new value is received three times consecutively or it is preceded by one of rules\ 3, 4 or 5. .LP 3) If the majority of the I\(hybits of the pointer word are inverted, a positive justification is indicated. Subsequent pointer values shall be incremented by one. .bp .LP 4) If the majority of the D\(hybits of the pointer word are inverted, a negative justification is indicated. Subsequent pointer values shall be decremented by one. .LP 5) If the NDF is set to 1001, then the coincident pointer value shall replace the current one at the offset indicated by the new pointer value regardless of the state of the receiver. .sp 1P .LP 3.3 \fITU\(hy1/TU\(hy2 pointers\fR .sp 9p .RT .PP The TU\(hy1 pointer is only used with floating mapping. Floating and locked modes of operation are described in \(sc\ 5.2. .PP The TU\(hy1 and TU\(hy2 pointers provide a method of allowing flexible and dynamic alignment of the VC\(hy1/VC\(hy2 within the TU\(hy1 and TU\(hy2 multiframes, independent of the actual contents of the VC. .RT .sp 1P .LP 3.3.1 \fITU\(hy1/TU\(hy2 pointer location\fR .sp 9p .RT .PP The TU\(hy1/TU\(hy2 pointers are contained in the V1 and V2 bytes as illustrated in Figure\ 3\(hy13/G.709. .RT .LP .rs .sp 37P .ad r \fBFigure 3\(hy13/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 3.3.2 \fITU\(hy1/TU\(hy2 pointer value\fR .sp 9p .RT .PP The TU pointer word is shown in Figure 3\(hy14/G.709. .PP The pointer value (bits 7\(hy16) is a binary number which indicates the offset from V2 to the first byte of the VC\(hy1/VC\(hy2. The range of the offset is different for each of the TU sizes as illustrated in Figure\(hy3\(hy15/G.709. Note that the pointer bytes are not counted in the offset calculation. .RT .LP .rs .sp 47P .ad r \fBFigure 3\(hy14/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 2\(hy15/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 3.3.3 \fITU\(hy1/TU\(hy2 multiframe indication byte\fR .sp 9p .RT .PP TU\(hy1/TU\(hy2 multiframe indication byte (H4) relates to the lowest level of multiplexing structure and indicates a variety of different multiframes for use by certain payloads. Specifically it provides: .RT .LP \(em 500 \(*ms (4\(hyframe) multiframe identifying frames containing TU\(hy1/TU\(hy2 pointers in the floating TU\(hy1/TU\(hy2 mode, and reserved byte locations in the locked TU\(hy1 mode; .LP \(em 2\ ms (16\(hyframe) multiframe for byte synchronous out\(hyslot\(hysignalling for 2048 kbitB/Fs payloads in the locked TU\(hy1 mode; .LP \(em 3 ms (24\(hyframe) multiframe for byte synchronous out\(hyslot\(hysignalling for 1544 kbitB/Fs payloads in the locked TU\(hy1 mode. .PP The coding of the H4 byte is illustrated in Figures\ 3\(hy16/G.709 to 3\(hy18/G.709. .RT .LP .rs .sp 41P .ad r \fBFigure 3\(hy16/G.709, p. 40\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 3\(hy17/G.709 [T3.709], p. 41\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 15P .ad r \fBFigure 3\(hy18/G.709 [T4.709], p. 42\fR .sp 1P .RT .ad b .RT .PP For network elements that operate only in the floating TU\(hy1/TU\(hy2 mode, a simplified multiframe alignment byte may be used. The simplified version provides only the 500 \(*ms multiframe. The 2 or 3\ ms multiframe of any signalling within floating TU\(hy1s is indicated by per\(hyTU multiframe indicators carried within the TU\(hy1. Figure\ 3\(hy13/G.709 shows the VC\(hy1/VC\(hy2 mapping in the multiframed TU\(hy1/TU\(hy2. .PP A converter from locked to floating TUs is permitted to pass H4 through transparently. A converter from floating to locked TUs must recover and align the multiframes from all of the floating TUs, and thus can transmit any convenient full multiframe on the locked TU side. .RT .sp 1P .LP 3.3.4 \fITU\(hy1/TU\(hy2 frequency justification\fR .sp 9p .RT .PP The TU\(hy1/TU\(hy2 pointer is used to frequency justify the VC\(hy1/VC\(hy2 exactly the same way that the TU\(hy3 pointer is used to frequency justify the VC\(hy3. A positive justification opportunity immediately follows the V3\ byte. .PP Additionally, V3 serves as the negative justification opportunity such that when the opportunity is taken, V3 is overwritten by data. This is also shown in Figure\ 3\(hy15/G.709. The indication of whether or not a justification opportunity has been taken is provided by the I\(hy and D\(hybits of the pointer in the current TU multiframe. The value contained in V3 when not being used for a negative justification is not defined. The receiver is required to ignore the value contained in V3 whenever it is not used as negative justification. .RT .sp 1P .LP 3.3.5 \fITU\(hy1/TU\(hy2 sizes\fR .sp 9p .RT .PP Bits 5 and 6 of TU\(hy1/TU\(hy2 pointer indicate the size of the TU. Four sizes are currently provided as shown in Table\ 3\(hy1/G.709. .RT .ce \fBH.T. [T1.709]\fR .ce TABLE\ 3\(hy1/G.709 .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(60p) | cw(60p) | cw(60p) . Size (binary) Designation { TU pointer range (in 500 \(*ms) } _ .T& cw(60p) | cw(60p) | cw(60p) . 01 TU\(hy22 0 \*`a 571 .T& cw(60p) | cw(60p) | cw(60p) . 00 TU\(hy21 0 \*`a 427 .T& cw(60p) | cw(60p) | cw(60p) . 10 TU\(hy12 0 \*`a 139 .T& cw(60p) | cw(60p) | cw(60p) . 11 TU\(hy11 0 \*`a 103 _ .TE .nr PS 9 .RT .ad r \fBTable 3\(hy1/G.709 [T1.709], p.\fR .sp 1P .RT .ad b .RT .PP Note that this technique is only used at the TU\(hy1/TU\(hy2 levels. .bp .sp 1P .LP 3.3.6 \fINew data flag (NDF)\fR .sp 9p .RT .PP Bits 1\(hy4 (N\(hybits) of the pointer word carry an NDF. It is the mechanism which allows an arbitrary change of the value of a pointer, and possibly also the size of the TU, if that change is due to a change in the payload. If the change includes a change in size then, implicitly, there must be a simultaneous new data transition in all of the TUs in the TUG\(hy21. .PP As with the TU\(hy3 pointer NDF, the normal value is 0110 (transmitted), and the value 1001 (received exactly) indicates a new alignment for the VC, and possibly a new size. If a new size is indicated, then all TU pointers (1 to 4) in the TUG\(hy21 must simultaneously indicate NDF with the same new size. The new alignment, and possibly size, is indicated by the pointer value and size value accompanying the NDF and takes effect at the offset indicated. The NDF should be enabled when the pointer value transits between its normal value and the concatenation indication (CI). .RT .sp 1P .LP 3.3.7 \fITU concatenation\fR .sp 9p .RT .PP TU\(hy2s may be concatenated to form a TU\(hy2\(hymc (concatenated m \(mu TU\(hy2s) to carry payloads requiring a capacity of more than a C\(hy21 (for the TU\(hy21 case) or C\(hy22 (for the TU\(hy22 case). A CI (1001 in bits\ 1\(hy4, bits\ 5\(hy6 unspecified, and all 1s in bits\ 7\(hy16 of the TU\(hy2 pointer) is used to show that this multi\(hyC\(hy2 payload, carried in a single VC\(hy2\(hymc (concatenated m\ \(mu\ VC\(hy2), must be kept together. .PP Note that the TU\(hy2 is carried in a TUG\(hy2 as shown in Figure 5\(hy4/G.709 and Figure\ 5\(hy5/G.709. .PP If a TU\(hy2 pointer contains the concatenation indication, then the pointer processor determines that this TU\(hy2 is concatenated to the previous TU\(hy2, and all operations indicated by the previous TU\(hy2 pointer are to be performed on this TU\(hy2 as well. .RT .sp 1P .LP 3.3.8 \fITU pointer generation and interpretation\fR .sp 9p .RT .PP The rules for generating and interpreting the TU\(hy1/TU\(hy2 pointer for the VC\(hy1/VC\(hy2 are an extension to the rules provided in \(sc\(sc\ 3.2.5 and 3.2.6 for the TU\(hy3 pointer with the following modifications: .RT .LP 1) The term TU\(hy3 is replaced with TU\(hy1/TU\(hy2 and the term VC\(hy3 is replaced with VC\(hy1/VC\(hy2. .LP 2) Additional pointer generation rule 6: If the size of the TU within a TUG\(hy21 is to change, then an NDF, as described in rule\ 5, is to be sent in all TUs of the new size in the group simultaneously. .LP 3) Additional pointer interpretation rule 6: If an NDF of 1001 and an arbitrary new size of TU are received simultaneously in all of the TUs within a TUG\(hy21, then the coincident pointers and sizes shall replace the current ones immediately. .sp 1P .LP 3.4 \fIPointer operation for STM\(hy1 concatenation\fR .sp 9p .RT .PP A concatenation indication contained in the AU\(hy4 pointer is used to show that the STM\(hy1 is part of an STM\(hyNc. .PP The AU\(hy4 within the first STM\(hy1 of an STM\(hyNc shall have a normal range of pointer values. All subsequent AU\(hy4s within the grouped STM\(hyNc shall have their pointer values set to 1001 in bits\ 1\(hy4, bits\ 5\(hy6 unspecified, and all 1s in bits\ 7\(hy16. Since this value does not indicate a valid offset, the pointer processors shall interpret this value to mean that they shall perform the same operations as performed on the first AU\(hy4 of the grouped STM\(hyNc. The NDF must be set when changing a pointer to/from the concatenation value. .RT .sp 1P .LP 3.4.1 \fIPointer generation\fR .sp 9p .RT .PP The following additional pointer generation rule shall apply for AU\(hy4 pointers: .PP If an STM\(hyNc signal is being transmitted, a pointer is generated for the AU\(hy4 within the first STM\(hy1 only. The concatenation indication is generated in place of the other pointers; all operations indicated by the AU\(hy4 pointer in the first STM\(hy1 apply to each STM\(hy1 in the STM\(hyNc. .bp .RT .sp 1P .LP 3.4.2 \fIPointer interpretation\fR .sp 9p .RT .PP The following additional pointer interpretation rule shall apply for AU\(hy4 pointers: .PP If the pointer contains the concatenation indication, then the operations performed on the STM\(hy1 are identical to those performed on the first STM\(hy1 within the STM\(hyNc. Rules\ 3 and 4 of \(sc\ 3.1.6 do not apply to this pointer. .RT .sp 2P .LP \fB4\fR \fBPath overhead\fR .sp 1P .RT .sp 1P .LP 4.1 \fIVC\(hy1/VC\(hy2 path overhead\fR .sp 9p .RT .PP The first byte in the VC\(hy1/VC\(hy2 pointed to by the TU\(hy1/TU\(hy2 pointer is the VC\(hy1/VC\(hy2 path overhead byte. This byte is designated as V5. .PP This byte provides the functions of error checking, signal, label and path status of the VC\(hy1/VC\(hy2 paths. The bit assignments of the VC\(hy1/VC\(hy2 POH are specified in the following paragraphs and are illustrated in Figure\ 4\(hy1/G.709. .PP V5 is used only in floating mode VC\(hy1/VC\(hy2s and is designated as an R\(hybyte in locked mode VC\(hy1/VC\(hy2s. Floating mode and locked mode operation is described in \(sc\ 5.8. .PP Bits 1 and 2 are used for error performance monitoring. A bit interleaved parity (BIP) scheme is specified. Bit 1 is set such that parity of all odd number bits (1, 3, 5 and 7) in all bytes in the previous VC\(hy1/VC\(hy2 is even and bit\ 2 is set similarly for the even number bits (2, 4, 6 and 8). Note that the calculation of the BIP\(hy2 includes the VC\(hy1/VC\(hy2 POH bytes but excludes the TU\(hy1/TU\(hy2 pointers. .PP Bit 3 is a VC\(hy1B/FVC\(hy2 path far\(hyend\(hyblock\(hyerror (FEBE) indication that is set to 1 and sent back towards a VC\(hy1/VC\(hy2 path originator if one or more errors were detected by the BIP\(hy2, and is otherwise set to\ 0. .PP Bit 4 is unused (X). The receiver is required to ignore the value of this bit. .PP Bits\ 5 through 7 provide a VC\(hy1/VC\(hy2 signal label. Eight binary values are possible in these three bits. Value\ 0 indicates \*QVC\(hy1/VC\(hy2 path unequipped\*U, and value\ 1 indicates \*QVC\(hy1/VC\(hy2 path equipped \(em\ non\(hyspecific payload\*U. The remaining six values are reserved to be defined as required in specific VC\(hy1/VC\(hy2 mappings. Any value received, other than 0, indicates an equipped VC\(hy1/VC\(hy2 path. .PP Bit 8 is a VC\(hy1/VC\(hy2 path remote alarm indication. This bit is set to a 1 if either a TU\(hy1/TU\(hy2 path alarm indication signal (AIS) or a signal failure condition is being received, otherwise it is set to\ 0. The VC\(hy1/VC\(hy2 path remote alarm indication is sent back by the VC\(hy1/VC\(hy2 assembler. .RT .LP .rs .sp 16P .ad r \fBFigure 4\(hy1/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 4.2 \fIVC\(hy3/VC\(hy4 path overhead\fR .sp 9p .RT .PP The VC\(hy3/VC\(hy4 POH will be assigned to and remain with the payload until the payload is demultiplexed and will be used for functions that are necessary in transporting all VC\(hy3/VC\(hy4. Note that this does not preclude the allocation of other overhead in specific mappings (such as justification control for mapping asynchronous 44 | 36\ kbit/s signals). That type of overhead is payload specific whereas the POH defined in this section is payload independent. .PP The VC\(hy4/VC\(hy32 POH consists of nine bytes denoted J1, B2, C2, G1, F2, H4, Z1\(hyZ3. The VC\(hy31 POH consists of six bytes denoted J1, B3, C2, G1, G2, H4. .RT .sp 1P .LP 4.2.1 \fIVC\(hy3/VC\(hy4 path trace (J1)\fR .sp 9p .RT .PP This is the first byte in the VC; its location is indicated by the associated AU/TU pointer. This byte is used to repetitively transmit a 64\ byte, fixed length string so that a path receiving terminal can verify its continued connection to the intended transmitter. The content of the message is not constrained by this standard since it is assumed to be user programmable at both transmit and receive ends. .RT .sp 1P .LP 4.2.2 \fIPath BIP\(hy8 (B3)\fR .sp 9p .RT .PP One byte is allocated in each VC\(hy3 or VC\(hy4 for a path error monitoring function. This function shall be a BIP\(hy8 code using even parity. The path BIP\(hy8 is calculated over all bits of the previous VC\(hy3 or VC\(hy4 before scrambling. The computed BIP\(hy8 is placed in the B3 byte of the VC\(hy3 or VC\(hy4 before scrambling. .RT .sp 1P .LP 4.2.3 \fISignal label (C2)\fR .sp 9p .RT .PP One byte is allocated to indicate the composition of the VC\(hy3/VC\(hy4. Of the 256 possible binary values, two are defined here and the remaining 254 values are reserved to be defined as required in specific VC\(hy3/VC\(hy4 mappings. .RT .LP \(em Value 0 indicates \*QVC\(hy3/VC\(hy4 path unequipped\*U. This value shall be originated if the section is complete but there is no VC\(hy3/VC\(hy4 path originating equipment. .LP \(em Value 1 indicates \*QVC\(hy3/VC\(hy4 path equipped \(em\ non\(hyspecific payload\*U. This value can be used for all payloads that need no further differentiation, or that achieve differentiation by other means such as messages from an operations system. .PP Note that any value received, other than value 0, constitutes an \*Uequipped\*U condition. .sp 1P .LP 4.2.4 \fIPath status (G1)\fR .sp 9p .RT .PP One byte is allocated to convey back to a VC\(hy3/VC\(hy4 path originator the path terminating status and performance. This feature permits the status and performance of the complete duplex path to be monitored at either end, or at any point along that path. As illustrated in Figure\ 4\(hy2/G.709, bits\ 1 through 4 convey the count of interleaved\(hybit blocks that have been detected in error by the path BIP\(hy8 code\ (B3). This count has nine legal values, namely 0\(hy8 errors. The remaining seven possible values represented by these four bits can only result from some unrelated condition and shall be interpreted as zero errors. VC\(hy3/VC\(hy4 path remote alarm indication is sent back by the VC\(hy3/VC\(hy4 assembler whenever the VC\(hy3/VC\(hy4 assembler is not receiving a valid signal. The VC\(hy3/VC\(hy4 path remote alarm indication is bit\ 5, which is set to one to indicate VC\(hy3/VC\(hy4 path remote alarm and is otherwise set to zero. The specific received conditions under which VC\(hy3/VC\(hy4 path remote alarm is initiated are path AIS, signal failure conditions or path tracer mismatch. Bits\ 6, 7 and\ 8 are not used. .RT .sp 1P .LP 4.2.5 \fIPath user channel (F2)\fR .sp 9p .RT .PP One byte is allocated for user communication purposes between path elements. .RT .sp 1P .LP 4.2.6 \fIMultiframe indicator (H4)\fR .sp 9p .RT .PP This byte provides a generalized multiframe indicator for payloads. Currently, this indicator is only used for TUG\(hystructured payloads as described in \(sc\ 3.3.3. .RT .sp 1P .LP 4.2.7 \fISpare (Z3\(hyZ5)\fR .sp 9p .RT .PP Three bytes are allocated for future, as yet undefined, purposes. These bytes have no defined value. The receiver is required to ignore the value contained in these bytes. .bp .RT .LP .rs .sp 13P .ad r \fBFigure 4\(hy2/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 2P .LP \fB5\fR \fBMapping of tributaries into VCs\fR .sp 1P .RT .PP Accommodation of asynchronous and synchronous tributaries presently defined in Recommendation\ G.702 shall be possible. At the TU\(hy1/TU\(hy2 level, asynchronous accommodation utilizes only the floating mode, whereas synchronous accommodation utilizes both the locked and the floating mode. .PP Figure 5\(hy1/G.709 shows TU\(hy1 and TU\(hy2 sizes and formats. .RT .sp 2P .LP 5.1 \fIMapping of tributaries into VC\(hy4\fR .sp 1P .RT .sp 1P .LP 5.1.1 \fIAsynchronous 139 | 64 kbit/s\fR .sp 9p .RT .PP One 139 | 64 kbit/s signal can be mapped into a VC\(hy4 container of an STM\(hy1 frame as shown in Figures\ 5\(hy2/G.709 and 5\(hy3/G.709. .PP The VC\(hy4 container consists of nine bytes (1 column) path overhead (POH) plus a 9\ row by 260\ column payload structure as shown in Figure\ 5\(hy2/G.709. .PP This payload can be used to carry one 139 | 64 kbit/s signal: .RT .LP \(em Each of the nine rows is partitioned into 20 blocks, consisting of 13\ bytes each (Figure\ 5\(hy2/G.709). .LP \(em In each row one justification opportunity (S) bit and five justification control (C)\ bits are provided (Figure\ 5\(hy3/G.709). .LP \(em The first byte of one block consists of: .LP i) eight information (I) bits (byte W), or .LP ii) eight fixed stuff (R) bits (byte Y), or .LP iii) one justification control (C) bits, plus five fixed fixed stuff (R)\ bits, plus two overhead (O)\ bits (byte\ X), or .LP iv) six information (I) bits, plus one justification opportunity (S)\ bit, plus one fixed stuff (R)\ bit, (byte\ Z). .LP \(em The last 12 bytes of one block consists of information bits\ (I). .PP The sequence of all these bytes is shown in Figure\ 5\(hy3/G.709. .PP The overhead (O) bits are reserved for further overhead communication purposes. .PP The set of five justification control (C) bits in every row is used to control the corresponding justification opportunity (S)\ bit. C\ C\ C\ C\ C\ =\ 0\ 0\ 0\ 0\ 0 indicates that the S bit is an information bit, whereas C\ C\ C\ C\ C\ =\ 1\ 1\ 1\ 1\ 1 indicates that the S bit is a justification bit. Majority vote should be used to make the justification decision in the desynchronizer for protection against single and double bit errors in the C\ bits. .PP The value contained in the S bit when used as justification bit is not defined. The receiver is required to ignore the value contained in this bit whenever it is used as a justification bit. .bp .RT .LP .rs .sp 47P .ad r \fBFigura 5\(hy1/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 22P .ad r \fBFigura 5\(hy2/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .rs .sp 27P .ad r \fBFigura 5\(hy3/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 5.1.2 \fITUG\(hy22\fR .sp 9p .RT .PP Sixteen TUG\(hy22s can be mapped into a VC\(hy4. This is illustrated in three\(hydimensional form in\ a) of Figure\ 5\(hy4/G.709 and in linear form in\ b) of Figure\ 5\(hy4/G.709. .RT .LP .rs .sp 47P .ad r \fBFigure 5\(hy4/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 5.1.3 \fITUG\(hy21\fR .sp 9p .RT .PP Twenty\(hyone TUG\(hy21s can be mapped into a VC\(hy4. This is shown in three\(hydimensional form in\ a) of Figure\ 5\(hy5/G.709 and in linear form in\ b) of Figure\ 5\(hy5/G.709. .RT .LP .rs .sp 47P .ad r \fBFigure 5\(hy5/G.709, p. 50\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 5.1.4 \fITU\(hy32\fR .sp 9p .RT .PP Three TU\(hy32s can be mapped into a VC\(hy4. This is illustrated in Figure\ 5\(hy6/G.709. .RT .LP .rs .sp 22P .ad r \fBFigure 5\(hy6/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 5.1.5 \fITU\(hy31\fR .sp 9p .RT .PP Four TU\(hy31s can be mapped into a VC\(hy4. This is illustrated in Figure\ 5\(hy7/G.709. .RT .LP .rs .sp 22P .ad r \fBFigure 5\(hy7/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 2P .LP 5.2 \fIMapping of tributaries into VC\(hy32\fR .sp 1P .RT .sp 1P .LP 5.2.1 \fIAsynchronous 44 | 36 kbit/s\fR .sp 9p .RT .PP One 44 | 36 kbit/s signal can be mapped into a VC\(hy32, as shown in Figure\ 5\(hy8/G.709. .PP The VC\(hy32 consists of nine subframes every 125 \(*ms. Each subframe consists of one byte of VC\(hy3 POH, 621 data bits, a set of five justification control bits, one justification opportunity bit and two overhead communication channel bits. The remaining bits are fixed stuff (R)\ bits. The O\ bits are reserved for future overhead communication purposes. .PP The set of five justification control (C) bits is used to control the justification opportunity (S)\ bit. C\ C\ C\ C\ C\ =\ 0\ 0\ 0\ 0\ 0 indicates that the S\ bit is a data bit, whereas C\ C\ C\ C\ C\ =\ 1\ 1\ 1\ 1\ 1 indicates that S\ bit is a justification bit. Majority vote should be used to make the justification decision in the desynchronizer for protection against single and double bit errors in the C\ bits. .PP The value contained in the S bit when used as justification bits is not defined. The receiver is required to ignore the value contained in this bit whenever it is used as a justification bit. .RT .LP .rs .sp 39P .ad r \fBFigure 5\(hy8/709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 5.2.2 \fITUG\(hy21\fR .sp 9p .RT .PP Seven TUG\(hy21s can be mapped into a VC\(hy32. This is illustrated in Figure\ 5\(hy9/G.709. The figure also illustrates the formation of the TUG\(hy21 from TU\(hy11, TU\(hy12 and TU\(hy21. .RT .LP .rs .sp 30P .ad r \fBFigure 5\(hy9/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 2P .LP 5.3 \fIMapping of tributaries into VC\(hy31\fR .sp 1P .RT .sp 1P .LP 5.3.1 \fIAsynchronous 34 | 68 kbit/s\fR .sp 9p .RT .PP One 34 | 68 kbit/s signal can be mapped into a VC\(hy31 as shown in Figure\ 5\(hy10/G.709. .PP In addition to the VC\(hy31 POH, the VC\(hy31 consists of a payload of 9\ \(mu\ 64\ bytes every 125\ \(*ms. This payload is divided in three subframes, each subframe divided in 12\ sectors and consisting of: .RT .LP \(em 1431 information (I) bits. .LP \(em two sets of five justification control bits (C\d1\u, C\d2\u). .LP \(em two justification opportunity bits (S\d1\u, S\d2\u). .LP \(em 93 fixed stuff bits (R). .PP Two sets (C\d1\u, C\d2\u) of five justification control bits are used to control the two justification opportunity bits\ S\d1\uand S\d2\urespectively. .PP C\d1\uC\d1\uC\d1\uC\d1\uC\d1\u= 0 0 0 0 0 indicates that S\d1\uis a data bit while C\d1\uC\d1\uC\d1\uC\d1\uC\d1\u\ =\ 1 1 1 1 1 indicates that S\d1\uis a justification bit. C\d2\u\ bits control S\d2\uin the same way. Majority vote should be used to make the justification decision in the desynchronizer for protection against single and double bit errors in the C\ bits. .bp .PP The value contained in S\d1\uand S\d2\uwhen they are justification bits is not defined. The receiver is required to ignore the value contained in these bits whenever they are used as justification bits. .PP \fINote\fR \ \(em\ The same mapping could be used for bit or byte synchronous 34 | 68\ kbit/s. In these cases, S\d1\u\ bit should be a fixed stuff and the S\d2\u\ bit an information bit. By setting the C\d1\u\ bits to\ 1 and the C\d2\u\ bits to\ 0, a common desynchronizer could be used for both asynchronous and synchronous 34 | 68\ kbit/s. .RT .LP .rs .sp 24P .ad r \fBFigure 5\(hy10/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 5.3.2 \fITUG\(hy22\fR .sp 9p .RT .PP Four TUG\(hy22s can be mapped into a VC\(hy31. This is illustrated in Figure\ 5\(hy11/G.709. The figure also illustrates the formation of the TUG\(hy22 from TU\(hy11, TU\(hy12 and TU\(hy22. .RT .sp 1P .LP 5.3.3 \fITUG\(hy21\fR .sp 9p .RT .PP Five TUG\(hy21s can be mapped into a VC\(hy31. This is illustrated in Figure\ 5\(hy12/G.709. The figure also illustrates the formation of the TUG\(hy21 from TU\(hy11, TU\(hy12 and TU\(hy21. .RT .sp 2P .LP 5.4 \fIMapping of tributaries into VC\(hy22\fR .sp 1P .RT .sp 1P .LP 5.4.1 \fIAsynchronous 8448 kbit/s\fR .sp 9p .RT .PP One 8448 kbit/s signal can be mapped into a VC\(hy22. Figure\ 5\(hy13/G.709 shows this over a period of 500\ \(*ms. .PP In addition to the VC\(hy22 POH, the VC\(hy22 consists of: .RT .LP \(em 4220 information (I) bits. .LP \(em 24 justification control bits (C\d1\u, C\d2\u). .LP \(em eight justification opportunity bits (S\d1\u, S\d2\u). .LP \(em 316 fixed stuff (R) bits. .bp .LP .rs .sp 26P .ad r \fBFigure 5\(hy11/G.709, p. 56\fR .sp 1P .RT .ad b .RT .LP .rs .sp 21P .ad r \fBFigure 5\(hy12/G.709, p. 57\fR .sp 1P .RT .ad b .RT .LP .bp .PP Two sets (C\d1\u, C\d2\u) of three justification control bits are used to control the two justification opportunity bits\ S\d1\uand\ S\d2\urespectively. .PP C\d1\uC\d1\uC\d1\u= 0 0 0 indicates that S\d1\uis a data bit while C\d1\uC\d1\uC\d1\u\ =\ 1 1 1 indicates that S1 is a justification bit. C\d2\u\ bits control S\d2\uin the same way. Majority vote should be used to make the justification decision in the desynchronizer for protection against single bit error in the C\ bits. .PP The value contained in S\d1\uand S\d2\uwhen they are justification bits is not defined. The receiver is required to ignore the value contained in these bits whenever they are used as justification bits. .RT .LP .rs .sp 35P .ad r \fBFigure 5\(hy13/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 5.4.2 \fISynchronous 8448 kbit/s\fR .sp 9p .RT .PP One bit or byte synchronous 8448 kbitB/Fs signal can be mapped into a VC\(hy22. Figure\ 5\(hy14/G.709 shows this over a period of 500\ \(*ms. .PP \fINote\fR \ \(em\ A common desynchronizer can be used for both asynchronous and synchronous mappings. .bp .RT .LP .rs .sp 28P .ad r \fBFigure 5\(hy14/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 2P .LP 5.5 \fIMapping of tributaries into VC\(hy21\fR .sp 1P .RT .sp 1P .LP 5.5.1 \fIAsynchronous 6312 kbit/s\fR .sp 9p .RT .PP One 6312 kbit/s signal can be mapped into a VC\(hy21. Figure\ 5\(hy15/G.709 shows this over a period of 500\ \(*ms. .PP In addition to the VC\(hy2 POH, the VC\(hy21 consists of 3152 data bits, 24 justification control bits, eight justification opportunity bits and 32\ overhead communication channel bits. The remaining bits are fixed stuff\ (R). The O\ bits are reserved for future overhead communication purposes. .PP Two sets (C\d1\u, C\d2\u) of three justification control bits are used to control the two justification opportunities S\d1\uand S\d2\urespectively. C\d1\uC\d1\uC\d1\u\ =\ 0 0 0 indicates that S\d1\uis a data bit while .PP C\d1\uC\d1\uC\d1\u\ =\ 1 1 1 indicates that S\d1\uis a justification bit. C\d2\ucontrols S\d2\uin the same way. Majority vote should be used to make the justification decision in the desynchronizer for protection against single bit errors in the C\ bits. .PP The value contained in S\d1\uand S\d2\uwhen they are justification bits is not defined. The receiver is required to ignore the value contained in these bits whenever they are used as justification bits. .RT .sp 1P .LP 5.5.2 \fIBit synchronous 6312 kbit/s\fR .sp 9p .RT .PP The bit synchronous mapping for 6312 kbit/s tributary is shown in Figure\ 5\(hy16/G.709. .PP Note that a common desynchronizer can be used for both asynchronous and bit synchronous mapping. .bp .RT .LP .rs .sp 25P .ad r \fBFigure 5\(hy15/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .rs .sp 25P .ad r \fBFigure 5\(hy16/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 5.5.3 \fIByte synchronous 6312 kbit/s\fR .sp 9p .RT .PP Under study. .RT .sp 2P .LP 5.6 \fIMapping of tributaries into VC\(hy12\fR .sp 1P .RT .sp 1P .LP 5.6.1 \fIAsynchronous 2048 kbit/s\fR .sp 9p .RT .PP One 2048 kbit/s signal can be mapped into a VC\(hy12. Figure\ 5\(hy17/G.709 shows this over a period of 500\ \(*ms. .PP In addition to the VC\(hy1 POH, the VC\(hy12 consists of 1023 data bits, six justification control bits, two justification bits and eight overhead communication channel bits. The remaining bits are fixed stuff (R)\ bits. The O\ bits are reserved for future overhead communication purposes. .PP Two sets (C\d1\u, C\d2\u) of three justification control bits are used to control the two justification opportunities S\d1\uand S\d2\urespectively.\fR C\d1\uC\d1\uC\d1\u\ =\ 0 0 0 indicates that S\d1\uis a data bit while C\d1\uC\d1\uC\d1\u\ =\ 1 1 1 indicates that S\d1\uis a justification bit. C\d2\ucontrols S\d2\uin the same way. Majority vote should be used to make the justification decision in the desynchronizer for protection against single bit errors in the C\ bits. .PP The value contained in S\d1\uand S\d2\uwhen they are justification bits is not defined. The receiver is required to ignore the value contained in these bits whenever they are used as justification bits. .RT .LP .rs .sp 32P .ad r \fBFigure 5\(hy17/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 5.6.2 \fIBit synchronous 2048 kbit/s\fR .sp 9p .RT .PP The bit synchronous mapping for 2048 kbit/s tributaries is shown in Figure\ 5\(hy18/G.709. .PP Note that a common desynchronizer can be used for both asynchronous and bit synchronous mappings. .RT .LP .rs .sp 36P .ad r \fBFigure 5\(hy18/G.709, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 5.6.3 \fIByte synchronous mapping for 2048 kbit/s\fR .sp 9p .RT .PP Figure 5\(hy19/G.709 shows byte synchronous mapping for 30\(hychannel 2048\ kbit/s tributaries employing Channel Associated Signalling (CAS). Signalling is carried in byte 19. The signalling assignments are shown in Figure\ 5\(hy20/G.709. .PP The S\d1\u, S\d2\u, S\d3\uand S\d4\ubits contain the signalling for the 30\ \(mu\ 64\ kbit/s channels. The phase of the signalling bits is indicated in the P\d1\uand P\d0\u\ bits in floating TU mode, and in the multiframe indicator byte (H4) in locked TU mode. This is illustrated in Figure\ 5\(hy20/G.709. .PP Byte synchronous mapping of 31 channel tributaries is shown in Figure\ 5\(hy21/G.709. Byte\ 19 carries tributary channel\ 16. .bp .RT .LP .rs .sp 32P .ad r \fBFigure 5\(hy19/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .rs .sp 15P .ad r \fBFigure 5\(hy20/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 5\(hy21/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 2P .LP 5.7 \fIMapping of tributaries into VC\(hy11\fR .sp 1P .RT .sp 1P .LP 5.7.1 \fIAsynchronous 1544 kbit/s\fR .sp 9p .RT .PP One 1544 kbit/s signal can be mapped into a VC\(hy11. Figure\ 5\(hy22/G.709 shows this over a period of 500\ \(*ms. .PP In addition to the VC\(hy1 POH, the VC\(hy11 consists of 771 data bits, six justification control bits, two justification opportunity bits and eight overhead communication channel bits. The remaining bits are fixed stuff (R)\ bits. The eight O\ bits are reserved for future communication purposes. .PP Two sets (C\d1\u, C\d2\u) of three justification control bits are used to control the two justification opportunities, S\d1\uand S\d2\urespectively. C\d1\uC\d1\uC\d1\u\ =\ 0 0 0 indicates that S\d1\uis a data bit while C\d1\uC\d1\uC\d1\u\ =\ 1 1 1 indicates that S\d1\uis a justification bit. C\d2\ucontrols S\d2\uin the same way. Majority vote should be used to make the justification decision in the desynchronizer for protection against single bit errors in the C\ bits. .PP The value contained in S\d1\uand S\d2\uwhen they are justification bits is not defined. The receiver is required to ignore the value contained in these bits whenever they are used as justification bits. .RT .LP .rs .sp 37P .ad r \fBFigure 5\(hy22/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 5.7.2 \fIBit synchronous 1544 kbit/s\fR .sp 9p .RT .PP The bit synchronous mapping for 1544 kbit/s tributaries is shown in Figure\ 5\(hy23/G.709. .PP Note that a common desynchronizer can be used for both asynchronous and bit synchronous mappings. .RT .LP .rs .sp 47P .ad r \fBFigure 5\(hy23/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 5.7.3 \fIByte synchronous mapping for 1544 kbit/s\fR .sp 9p .RT .PP The byte synchronous mapping for 1544 kbit/s is depicted in Figure\ 5\(hy24/G.709. .PP The S\d1\u, S\d2\u, S\d3\uand S\d4\ubits contain the signalling for the 24\ \(mu\ 64\ kbit/s channels. The phase of the signalling bits can be indicated in the P\d1\uand P\dO\u\ bits in floating TU mode, and in the multiframe indicator byte (H4) in locked mode. This is illustrated in Figure\ 5\(hy25/G.709. The usage of the PP\ bits has options, because the common signalling method and another channel associated signalling method (e.g.\ Recommendation\ G.704, \(sc\(sc\ 3.1.3 and 3.2.3) do not need the PP\ bits. The operations of the alternative channel associated signalling method is shown in Figure\ 5\(hy26/G.709. .RT .LP .rs .sp 44P .ad r \fBFigure 5\(hy24/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 47P .ad r \fBFigure 5\(hy25/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP .rs .sp 33P .ad r \fBFigure 5\(hy26/G.709 [T5.709], p.\fR .sp 1P .RT .ad b .RT .LP .bp .LP \fR .sp 1P .LP 5.8 \fIFloating and locked mode conversion\fR .sp 9p .RT .PP There are two possible multiplexing modes of the TU structures: floating and locked. .PP In the floating TU mode four consecutive 125\ \(*ms VC\(hyn frames are organized into a 500\ \(*ms multiframe, the phase of which is indicated by the multiframe indicator byte (H4) in the VC\(hy\fIn\fR \ POH. This 500\ \(*ms TU multiframe is shown in Figure\ 3\(hy13/G.709. .PP Locked TU mode of transport is a fixed mapping of synchronous structured payloads into a VC\(hy\fIn\fR . This provides a direct correspondence between subtending tributary information and the location of that information within the VC\(hy\fIn\fR . Since the tributary information is fixed and immediately identifiable with respect to the TU\(hy\fIn\fR or AU\(hy\fIn\fR pointer associated with the VC\(hy\fIn\fR , no TU pointers are available for payload usage. .PP Figure 5\(hy27/G.709 illustrates the conversion between floating and locked TU modes for each of the four TU sizes. Note that certain bytes\ (R) in the current set of mapping are not used in the floating mode in order that those mappings can be used in both floating and locked modes. Since the V1\(hyV4 and V5 bytes are reserved, the 500\ \(*ms TU multiframe is unnecessary. Therefore the role of the multiframe indicator byte (H4) in locked mode is to define 2 and 3\ ms signalling frames for byte synchronous mappings. .RT .LP .rs .sp 34P .ad r \fBFigure 5\(hy27/G.709, p.\fR .sp 1P .RT .ad b .RT .LP .bp