.rs .\" Troff code generated by TPS Convert from ITU Original Files .\" Not Copyright ( c) 1991 .\" .\" Assumes tbl, eqn, MS macros, and lots of luck. .TA 1c 2c 3c 4c 5c 6c 7c 8c .ds CH .ds CF .EQ delim @@ .EN .nr LL 40.5P .nr ll 40.5P .nr HM 3P .nr FM 6P .nr PO 4P .nr PD 9p .po 4P .rs \v | 5i' .sp 2P .LP \fBRecommendation\ G.704\fR .RT .sp 2P .ce 1000 \fBSYNCHRONOUS\ FRAME\ STRUCTURES\ USED\ AT\fR .EF '% Fascicle\ III.4\(em\ Rec.\ G.704'' .OF '''Fascicle\ III.4\(em\ Rec.\ G.704 %' .ce 0 .sp 1P .ce 1000 \fBPRIMARY\ AND\ SECONDARY\ HIERARCHICAL\ LEVELS\fR .ce 0 .sp 1P .ce 1000 \fI(Malaga\(hyTorremolinos, 1984; amended at Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .LP \fB1\fR \fBGeneral\fR .sp 1P .RT .PP This Recommendation gives functional characteristics of interfaces associated with: .RT .LP \(em network nodes, in particular, synchronous digital multiplex equipment and digital exchanges in IDNs for telephony and ISDNs, and .LP \(em PCM multiplexing equipment. .PP Paragraph 2 deals with basic frame structures, including details of frame length, frame alignment signals, cyclic redundancy check (CRC) procedures and other basic information. .PP Paragraphs 3 to 6 contain more specific information about how certain channels at 64\ kbit/s and at other bit rates are accomodated within the basic frame structures described in \(sc\ 2. .PP Electrical characteristics for these interfaces are defined in Recommendation\ G.703. .PP \fINote\ 1\fR \ \(em\ This Recommendation does not necessarily apply to those cases where the signals that cross the interfaces are devoted to non\(hyswitched connections, such as those for the transport of encoded wideband signals (e.g.\ broadcast TV signals or multiplexed sound\(hyprogramme signals which need not be individually routed via the ISDN), see also Annex\ A to Recommendation\ G.702. .PP \fINote\ 2\fR \ \(em\ The frame structures recommended in this Recommendation do not apply to certain maintenance signals, such as the all 1s signals transmitted during fault conditions or other signals transmitted during out\(hyof\(hyservice conditions. .PP \fINote\ 3\fR \ \(em\ Frame structures associated with digital multiplexing equipments using justification are covered in each corresponding equipment Recommendation. .PP \fINote\ 4\fR \ \(em\ Inclusion of channel structures at other bit rates than 64\ kbit/s is a matter for further study. Recommendations\ G.761 and\ G.763 dealing with the characteristics of PCM/ADPCM transcoding equipment contain information about channel structures at 32\ kbit/s. The more general use of those particular structures is a subject of further study. .RT .LP \fB2\fR \fBBasic frame\fR \fBstructures\fR .sp 1P .RT .sp 2P .LP 2.1 \fIBasic frame structure at 1544 kbit/s\fR .sp 1P .RT .sp 1P .LP 2.1.1 \fIFrame length\fR : .sp 9p .RT .PP 193 bits, numbered 1 to 193. The frame repetition rate is 8000\ Hz. .RT .sp 1P .LP 2.1.2 \fIF\(hybit\fR .sp 9p .RT .PP The first bit of a frame is designated an F\(hybit, and is used for such purposes as frame alignment, performance monitoring and providing a data link. .RT .sp 1P .LP 2.1.3 \fIAllocation of F\(hybit\fR .sp 9p .RT .PP Two alternative methods as given in Tables\ 1/G.704 and 2/G.704 for allocation of F\(hybits are recommended. .bp .RT .ce \fBH.T. [T1.704]\fR .ce TABLE\ 1/G.704 .ce \fBMultiframe structure for the 24 frame multiframe\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(36p) | cw(42p) sw(12p) sw(12p) sw(12p) | cw(36p) sw(42p) | lw(36p) , ^ | c | c s s | ^ | ^ , ^ | ^ | c | c | c | c | c | ^ . { Frame number within multiframe } F\(hybit { For character signal | ua\d\u)\d } Bit number within multiframe Assignements FAS DL { CRC Bit number(s) in each channel time slot } For signalling | ua\d\u)\d { Signalling channel designation | ua\d\u)\d } .T& lw(228p) . .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . \ 1 \ \ \ 1 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . \ 2 \ 194 \(em \(em \fIe\fR 1 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . \ 3 \ 387 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . \ 4 \ 580 0 \(em \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . \ 5 \ 773 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . \ 6 \ 966 \(em \(em \fIe\fR 2 1\(hy7 8 A .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . \ 7 1159 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . \ 8 1352 0 \(em \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . \ 9 1545 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 10 1738 \(em \(em \fIe\fR 3 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 11 1931 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 12 2124 1 \(em \(em 1\(hy7 8 B .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 13 2317 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 14 2510 \(em \(em \fIe\fR 4 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 15 2703 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 16 2896 0 \(em \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 17 3089 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 18 3282 \(em \(em \fIe\fR 5 1\(hy7 8 C .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 19 3475 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 20 3668 1 \(em \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 21 3861 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 22 4054 \(em \(em \fIe\fR 6 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 23 4247 \(em \fIm\fR \(em 1\(hy8 \(em \fB.\fR .T& cw(36p) | cw(42p) | cw(12p) | cw(12p) | cw(12p) | cw(36p) | cw(42p) | cw(36p) . 24 4440 1 \(em \(em 1\(hy7 8 D .TE .IP FAS Frame alignement signal (. | | 001011 . | | ). .IP DL 4 kbit/s data link (message bits \fIm\fR). .IP CRC CRC\(hy6 (block check field (check bits \fIe\fR 1 . | | \fIe\fR 6). .IP \ua\d\u)\d Only applicable in the case of channel associated signalling see (\(sc\ 3.1.3.2.) .nr PS 9 .RT .ad r \fBTableau 1/G.704 [T1.704], p. 1\fR .sp 1P .RT .ad b .RT .ce \fBH.T. [T2.704]\fR .ce TABLE\ 2/G.704 .ce \fBAllocation of F\(hybit for the 12\(hyframe multiframe\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; lw(48p) | lw(72p) | lw(72p) . .TE .nr PS 9 .RT .ad r \fBTableau 2/G.704 [T2.704], p. 2\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 2.1.3.1 \fIMethod 1: Twenty\(hyfour\(hyframe multiframe\fR .sp 9p .RT .PP Allocation of the F\(hybit to the multiframe alignment signal, the CRC check bits and the data link is given in Table\ 1/G.704. .RT .sp 1P .LP 2.1.3.1.1\ \ \ \fIMultiframe alignment signal\fR .sp 9p .RT .PP The F\(hybit of every fourth frame forms the pattern 001011\ . | | \ 001011. This multiframe alignment signal is used to identify where each particular frame is located within the multiframe in order to extract the cyclic redundancy check code, CRC\(hy6, and the data link information, as well as to identify those frames that contain signalling (frames\ 6, 12, 18 and\ 24), if channel associated signalling is used. .RT .sp 1P .LP 2.1.3.1.2\ \ \ \fICyclic redundancy check\fR .sp 9p .RT .PP The CRC\(hy6 is a method of performance monitoring that is contained within the F\(hybit position of frames\ 2, 6, 10, 14 18 and\ 22 of every multiframe (see Table\ 1/G.704). .PP The CRC\(hy6 message block check bits \fIe\fR\d1\u, \fIe\fR\d2\u, \fIe\fR\d3\u, \fIe\fR\d4\u, \fIe\fR\d5\u, and\ \fIe\fR\d6\uare contained within multiframe bits\ 194, 966, 1738, 2510, 3282 and\ 4054 respectively, as shown in Table\ 1/G.704. The CRC\(hy6 Message Block (CMB) is a sequence of 4632\ serial bits that is coincident with a multiframe. By definition, CMB\ \fIN\fR begins at bit position\ 1 of multiframe\ \fIN\fR and ends at bit position\ 4632 of multiframe\ \fIN\fR . The first transmitted CRC bit of a multiframe is the most significant bit of the CMB polynomial. .PP In calculating the CRC\(hy6 bits, the F\(hybits are replaced by binary 1s. All information in the other bit positions will be identical to the information in the corresponding multiframe bit positions. .PP The check\(hybit sequence \fIe\fR\d1\uthrough\ \fIe\fR\d6\utransmitted in multiframe\ \fIN\fR +1, is the remainder after multiplication by\ \fIx\fR \u6\d and then division (modulo\(hy2) by the generator polynomial\ \fIx\fR \u6\d+\fIx\fR +1 of the polynomial corresponding to CMB\ \fIN\fR . The first check bit (\fIe\fR\d1\u) is the most significant bit of the remainder; the last check bit .PP (\fIe\fR\d6\u) is the least significant bit of the remainder. Each multiframe contains the CRC\(hy6 check bits generated for the preceding CMB. .PP At the receiver, the received CMB, with each F\(hybit having first been replaced by a binary\ 1, is acted upon by the multiplication/division process described above. The resulting remainder is compared on a bit\(hyby\(hybit basis, with the CRC\(hy6 check bits contained in the subsequently received multiframe. The compared check bits will be identical in the absence of transmission errors. .RT .sp 1P .LP 2.1.3.1.3\ \ \fI4 kbit/s data link\fR .sp 9p .RT .PP Beginning with frame 1 of the multiframe (see Table\ 1/G.704) the first bit of every other frame is part of the 4\ kbit/s data link. This data link provides a communication path between primary hierarchical level terminals and will contain data, an idle data link sequence or a loss of frame alignment alarm sequence. .PP The format to be used for the transmission of data over the \fIm\fR \(hybits of the data link is still under study. .PP The idle data link pattern is also under study. .PP A loss of frame alignment alarm sequence is used when a loss of frame alignment (LFA) condition has been detected. After a loss of frame alignment condition is detectd at local end\ A, a 16\(hybit LFA sequence of eight 1s eight 0s (1111111100000000) will be transmitted in the \fIm\fR \(hybits of the 4\ kbit/s data link continuously to remote end\ B. .RT .sp 1P .LP 2.1.3.2 \fIMethod 2: Twelve\(hyframe multiframe\fR .sp 9p .RT .PP Allocation of the F\(hybit to the frame alignment signal, multiframe alignment signal and signalling is given in Table\ 2/G.704. .RT .sp 2P .LP 2.2 \fIBasic frame structure at 6312 kbit/s\fR .sp 1P .RT .sp 1P .LP 2.2.1 \fIFrame length\fR .sp 9p .RT .PP The number of bits per frame is 789. The frame repetition rate is 8000\ Hz. .RT .sp 1P .LP 2.2.2 \fIF\(hybits\fR .sp 9p .RT .PP The last five bits of a frame are designated as F\(hybits, and are used for such purposes as frame alignment, performance monitoring and providing a data link. .bp .RT .sp 1P .LP 2.2.3 \fIAllocation of F\(hybits\fR .sp 9p .RT .PP Allocation of the F\(hybits is given in Table\ 3/G.704. .RT .LP .rs .sp 19P .LP [T3.704]\fR .ad r \fBTable 3/G.704 [T3.704], p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 2.2.3.1 \fIFrame alignment signal\fR .sp 9p .RT .PP The frame and multiframe alignment signal is 110010100, and is carried on the F\(hybits in frames\ 1 and\ 2, excluding bit\ 789 of frame\ 1. .RT .sp 1P .LP 2.2.3.2 \fICyclic redundancy check\fR .sp 9p .RT .PP The cyclic redundancy check 5 (CRC\(hy5) message block (CMB) is a sequence of 3151\ serial bits which starts at bit number\ 1 of frame number\ 1 and ends at bit number\ 784 of frame number\ 4. The CRC\(hy5 message block check bits\ \fIe\fR\d1\u, \fIe\fR\d2\u, \fIe\fR\d3\u, \fIe\fR\d4\uand\ \fIe\fR\d5\uoccupy the last five bits of the multiframe as shown in Table\ 3/G.704. .PP The check\(hybit sequence \fIe\fR\d1\uthrough \fIe\fR\d5\utransmitted in multiframe\ \fIN\fR is the remainder after multiplication by\ \fIx\fR \u5\d and then division (modulo\(hy2) by the generator polynomial x\fR \u5\d+\fIx\fR \u4\d+\fIx\fR \u2\d+1 of the polynomial corresponding to CMB\ \fIN\fR . The first check bit (\fIe\fR\d1\u) is the most significant bit of the remainder; the last check bit (\fIe\fR\d5\u) is the least significant bit of the remainder. Each multiframe contains the CRC\(hy5\ check bits generated for the corresponding CMB. .PP At the receiver the incoming sequence of 3156 serial bits (i.e.\ 3151\ bits of CMB and 5\ CRC bits), when divided by the generator polynomials, will result in a remainder of\ 00000 in the absence of transmission errors. .RT .sp 1P .LP 2.2.3.3 \fI4 kbit/s data link\fR .sp 9p .RT .PP The bit \fIm\fR shown in Table\ 3/G.704 is used as a data link bit. These bits provide 4\ kbit/s data transmission capability associated with the 6312\ kbit/s digital path. .RT .sp 1P .LP 2.2.3.4 \fIRemote end alarm indication\fR .sp 9p .RT .PP After a loss of frame alignment condition is detected at local end\ A, remote end alarm signal bit\ \fIa\fR , shown in Table\ 3/G.704, will be transmitted to remote end\ B. .bp .RT .sp 2P .LP 2.3 \fIBasic frame structure at 2048 kbit/s\fR .sp 1P .RT .sp 1P .LP 2.3.1 \fIFrame length\fR .sp 9p .RT .PP 256 bits, numbered 1 to 256. The frame repetition rate is 8000\ Hz. .RT .sp 1P .LP 2.3.2 \fIAllocation of bits number 1 to 8 of the frame\fR .sp 9p .RT .PP Allocation of bits number 1 to 8 of the frame is shown in Table\ 4a/G.704. .RT .LP .rs .sp 31P .LP [T4.704]\fR .ad r \fBTable 4a/G.704 [T4.704], p.\fR .sp 1P .RT .ad b .RT .sp 2P .LP 2.3.3 \fIDescription of the\fR \fICRC\(hy4 procedure\fR \fIin bit 1 of the\fR \fIframe\fR .sp 1P .RT .sp 1P .LP 2.3.3.1 \fISpecial use of bit 1 of the frame\fR .sp 9p .RT .PP Where there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability, then bit\ 1 should be used for a Cyclic Redundancy Check\(hy4 (CRC\(hy4) procedure as detailed below. .PP \fINote\fR \ \(em\ Equipment incorporating the CRC\(hy4 procedure should be designed to be capable of interworking with equipment which does not incorporate the CRC procedure, with the option being manually selectable (e.g.\ by straps). For such interworking, bit\ 1 of the frame should be fixed at\ 1 in both directions (see Table\ 4a/G.704, Note\ 1). .bp .RT .PP 2.3.3.2 The allocation of bits 1 to 8 of the frame is shown in Table\ 4b/G.704 for a complete CRC\(hy4 multiframe. .sp 9p .RT .LP .rs .sp 28P .LP [T5.704]\fR .ad r \fBTable 4b/G.704 [T5.704], p.\fR .sp 1P .RT .ad b .RT .LP .sp 2 .PP 2.3.3.3 Each CRC\(hy4 multiframe, which is composed of 16 frames numbered 0\ to 15, is divided into two 8\(hyframe sub\(hymultiframes (SMF), designated SMF\ I and SMF\ II which signifies their respective order of occurrence within the CRC\(hy4 multiframe structure. The SMF is the Cyclic Redundancy Check\(hy4 (CRC\(hy4) block size (i.e.\ 2048\ bits). .sp 9p .RT .PP The CRC\(hy4 multiframe structure is not related to the possible use of a multiframe structure in 64\ kbit/s channel time slot\ 16 (see \(sc\ 5.1.3.2). .sp 1P .LP 2.3.3.4 \fIUse of bit 1 in 2048 kbit/s CRC\(hy4 multiframe\fR .sp 9p .RT .PP In those frames containing the frame alignment signal (defined in \(sc\ 2.3.2), bit\ 1 is used to transmit the CRC\(hy4 bits. There are four CRC\(hy4 bits, designated\ C\d1\u, C\d2\u, C\d3\uand\ C\d4\uin each SMF. .PP In those frames not containing the frame alignment signal (see \(sc\ 2.3.2), bit\ 1 is used to transmit the 6\(hybit CRC\(hy4 multiframe alignment signal and two CRC\(hy4 error indication bits\ (E). .bp .PP The CRC multiframe alignment signal has the form 001011. .PP The E\(hybits should be used to indicate received errored sub\(hymultiframes by setting the binary state of one E\(hybit from 1\ to\ 0 for each errored sub\(hymultiframe. Any delay between the detection of an errored sub\(hymultiframe and the setting of the E\(hybit that indicates the error state must be less than 1\ second. .PP \fINote\ 1\fR \ \(em\ The E\(hybits will always be taken into account even if the SMF which contains them is found to be errored, since there is little likelihood that the E\(hybits themselves will be errored. .PP \fINote\ 2\fR \ \(em\ In the short term, there may exist equipments which do not use the E\(hybits; in this case the E\(hybits are set to binary\ 1. .RT .sp 2P .LP 2.3.3.5\ \ \fICyclic Redundancy Check\fR .sp 1P .RT .sp 1P .LP 2.3.3.5.1\ \ \fIMultiplication/division process\fR .sp 9p .RT .PP A particular CRC\(hy4 word, located in sub\(hymultiframe \fIN\fR , is the remainder after multiplication by \fIx\fR \u4\d and then division (modulo\ 2) by the generator polynomial \fIx\fR \u4\d\ +\ \fIx\fR \ +\ 1, of the polynomial representation of sub\(hy multiframe \fIN\fR | (em | ). .PP \fINote\fR \ \(em\ When representing the contents of the check block as a polynomial, the first bit in the block, i.e.\ frame\ 0, bit\ 1 or frame\ 8, bit\ 1, should be taken as being the most significant bit. Similarly, C\d1\uis defined to be the most significant bit of the remainder and C\d4\uthe least significant bit of the remainder. .RT .sp 1P .LP 2.3.3.5.2\ \ \fIEncoding procedure\fR .sp 9p .RT .LP i) The CRC\(hy4 bits in the SMF are replaced by binary 0s. .LP ii) The SMF is then acted upon by the multiplication/division process referred to in \(sc\ 2.3.3.5.1. .LP iii) The remainder resulting from the multiplication/division process is stored, ready for insertion into the respective CRC\(hy4 locations of the next SMF. .PP \fINote\fR \ \(em\ The CRC\(hy4 bits thus generated do not affect the result of the multiplication/division process in the next SMF because, as indicated in\ i) above, the CRC\(hy4 bit positions in an SMF are initially set to\ 0 during the multiplication/division process. .sp 1P .LP 2.3.3.5.3\ \ \fIDecoding procedure\fR .sp 9p .RT .LP i) A received SMF is acted upon by the multiplication/division process referred to in \(sc\ 2.3.3.5.1, after having its CRC\(hy4 bits extracted and replaced by 0s. .LP ii) The remainder resulting from this division process is then stored and subsequently compared on a bit\(hyby\(hybit basis with the CRC bits received in the next SMF. .LP iii) If the remainder calculated in the decoder exactly corresponds to the CRC\(hy4 bits received in the next SMF, it is assumed that the checked SMF is error free. .sp 2P .LP 2.4 \fIBasic frame structure at 8448 kbit/s\fR .sp 1P .RT .sp 1P .LP 2.4.1 \fIFrame length\fR .sp 9p .RT .PP The number of bits per frame is 1056. They are numbered from 1\ to\ 1056. The frame repetition rate is 8000\ Hz. .RT .sp 1P .LP 2.4.2 \fIFrame alignment signal\fR .sp 9p .RT .PP The frame alignment signal is 11100110\ 100000 and occupies the bit\(hypositions 1\ to\ 8 and 529\ to\ 534. .RT .sp 1P .LP 2.4.3 \fIService digits\fR .sp 9p .RT .PP Bit 535 is used to convey alarm indication (bit 535 at 1 state \(em alarm; bits\ 535 at 0\ state \ =\ no alarm). .PP Bit 536 is left free for national use and should be fixed at 1 on paths crossing the international border. The same applies to bits\ 9\(hy40 in the case of channel\(hyassociated signalling. .bp .RT .LP \fB3\fR \fBCharacteristics of frame structure carrying channels at various bit rates in 1544 kbit/s\fR .sp 1P .RT .sp 2P .LP 3.1 \fIInterface at 1544 kbit/s carrying 64 kbit/s channels\fR .sp 1P .RT .sp 1P .LP 3.1.1 \fIFrame structure\fR .sp 9p .RT .sp 1P .LP 3.1.1.1 \fINumber of bits per 64 kbit/s channel time slot\fR .sp 9p .RT .PP Eight, numbered 1 to 8. .RT .sp 1P .LP 3.1.1.2 \fINumber of 64 kbit/s channel time slots per frame\fR .sp 9p .RT .PP Bits 2 to 193 in the basic frame carry 24 octet interleaved 64 kbit/s channel time slots, numbered 1\ to\ 24. .RT .sp 1P .LP 3.1.1.3 \fIAllocation of F\(hybit\fR .sp 9p .RT .PP Refer to \(sc\ 2.1.3. .RT .sp 1P .LP 3.1.2 \fIUse of 64 kbit/s channel time slots\fR .sp 9p .RT .PP Each 64 kbit/s channel time slot can accommodate e.g., a PCM encoded voiceband signal conforming to Rec.\ G.711 or data information with a bit rate up to 64\ kbit/s. .RT .sp 1P .LP 3.1.3 \fISignalling\fR .sp 9p .RT .PP Two alternative methods as given in \(sc\(sc\ 3.1.3.1 and\ 3.1.3.2 are recommended: .RT .sp 1P .LP 3.1.3.1 \fICommon channel signalling\fR .sp 9p .RT .PP One 64 kbit/s channel time slot is used to provide common channel signalling at a rate of 64\ kbit/s. In the case of the 12\(hyframe multiframe method of \(sc\ 2.1.3.2, the pattern of the S\(hybit may be arranged to carry common channel signalling at a rate of 4\ kbit/s or a sub\(hymultiple of this rate. .RT .sp 2P .LP 3.1.3.2\ \ \fIChannel associated signalling\fR .sp 1P .RT .sp 1P .LP 3.1.3.2.1\ \ \fIAllocation of signalling bits for the 24\(hyframe multiframe\fR .sp 9p .RT .PP As can be seen in Table\ 1/G.704, there are four different signalling bits (A, B, C and\ D) in the multiframe. This channel associated signalling can provide four independent 333\(hybit/s signalling channels designated\ A, B, C and\ D, two independent 667\(hybit/s signalling channels designated\ A and\ B (see Note,) or one 1333\(hybit/s signalling channel. .PP \fINote\fR \ \(em\ When only four state signalling is required, the A, B signalling bits previously associated with frames\ 6 and\ 12 respectively should be mapped into the A, B, C,\ D signalling bits of frames\ 6, 12, 18 and\ 24 respectively as follows: A=A, B=B, C=A, D=B. In this case the ABCD signalling is the same as the AB signalling specified in \(sc\ 3.1.3.2.2. .RT .sp 1P .LP 3.1.3.2.2\ \ \fIAllocation of signalling bits for the 12\(hyframe multiframe\fR .sp 9p .RT .PP Based on agreement between the Administrations involved, channel\(hyassociated signalling is provided for intra\(hyregional circuits according to the following arrangement: .PP A multiframe comprises 12 frames as shown in Table\ 5/G.704. The multiframe alignment signal is carried on the S\(hybit as shown in the table. .PP Frames 6 and 12 are designated as signalling frames. The eight bit in each channel time slot is used in every signalling frame to carry the signalling associated with that channel. .bp .RT .LP .rs .sp 24P .LP [T6.704]\fR .ad r \fBTable 5/G.704 [T6.704], p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 3.2 \fIInterface at 1544 kbit/s carrying 32 kbit/s channel time slots\fR (see Note) .sp 9p .RT .PP \fINote\fR \ \(em\ This interface provides for the carrying of 32 kbit/s information. The interface will be used between network nodes and will apply to primary rate multiplexing equipment, digital cross\(hyconnect equipment, transcoder and other equipment relevant to the network nodes. Switching in this case is assumed to take place on a 64\ kbit/s basis. .RT .sp 2P .LP 3.2.1 \fIFrame structure\fR .sp 1P .RT .sp 1P .LP 3.2.1.1 \fINumber of bits per 32 kbit/s channel time slot\fR .sp 9p .RT .PP Four, numbered 1 to 4. .RT .sp 1P .LP 3.2.1.2 \fINumber of 32 kbit/s channel time slots per frame\fR .sp 9p .RT .PP Bits 2 to 193 in the basic frame can carry forty\(hyeight 4\(hybit interleaved 32\ kbit/s channel time slots, numbered 1\ to\ 48. .RT .sp 1P .LP 3.2.1.3 \fIAllocation of F\(hybits\fR .sp 9p .RT .PP Refer to \(sc\ 2.1.3. .RT .sp 1P .LP 3.2.2 \fIUse of 32 kbit/s channel time slot\fR .sp 9p .RT .PP Each 32 kbit/s channel time slot can accomodate an ADPCM\(hyencoded voiceband signal conforming to Rec.\ G.721, or data with a bit rate up to 32\ kbit/s. .bp .RT .sp 2P .LP 3.2.3 \fI384 kbit/s 12\(hychannel time slot grouping\fR .sp 1P .RT .sp 1P .LP 3.2.3.1 \fIStructure of 12\(hychannel time slot grouping\fR .sp 9p .RT .PP The 1544 kbit/s frame for 32 kbit/s channel time slots shown in Table\ 6/G.704 is structured to provide four independent 384\ kbit/s 12\(hychannel time slot groupings. These are numbered 1\(hy4, and transmitted in numbered order starting with time slot grouping number\ 1. .PP The signalling grouping channels (SGC) for time slot groupings 1\(hy4, occupy time slots\ 12, 24, 36 and\ 48 respectively. Each time slot grouping can be independently configured for situations requiring channel associated signalling or situations with no signalling requirement (e.g.\ external common signalling). (See \(sc\ 3.2.3.1.1.) .RT .LP .rs .sp 15P .LP [T7.704]\fR .ad r \fBTable 6/G.704 [T7.704], p.\fR .sp 1P .RT .ad b .RT .LP .sp 1 .sp 1P .LP 3.2.3.1.1\ \ \fIUse of a 384 kbit/s time slot grouping\fR .sp 9p .RT .PP Use of a 384 kbit/s time slot grouping is categorized into two possible configurations: .RT .LP \(em When no signalling capabilities are required, a 384 kbit/s time slot grouping can carry twelve 32\ kbit/s channel time slots; .LP \(em When channel associated signalling capabilities are required, a 384\ kbit/s time slot grouping will consist of eleven 32\ kbit/s channel time slots and a 32\ kbit/s channel time slot defined as a signalling grouping channel. .sp 1P .LP 3.2.3.1.2\ \ \fIUse of a\fR \fIsignalling grouping channel\fR .sp 9p .RT .PP A signalling grouping channel is used for the transmission of channel associated A\(hyB\(hyC\(hyD signalling information, signalling grouping channel alarm information, the signalling grouping channel multiframe alignment signal, and CRC\(hy6 error detection information between network nodes. .RT .sp 2P .LP 3.2.4 \fI32 kbit/s signalling grouping channel multiframe structure\fR .sp 1P .RT .sp 1P .LP 3.2.4.1 \fINumber of bits per 32 kbit/s signalling grouping channel time\fR \fIslot\fR .sp 9p .RT .PP Four, numbered 1 to 4. .bp .RT .sp 1P .LP 3.2.4.2 \fIBit allocation of 32 kbit/s signalling grouping channel time\fR \fIslot\fR .sp 9p .RT .PP Allocated to the last four bits of each time slot grouping. .RT .sp 1P .LP 3.2.4.3 \fIMultiframe structure\fR .sp 9p .RT .PP The signalling grouping channel multiframe structure consists of 24\ consecutive frames numbered 1\ to\ 24. Table\ 7/G.704 shows the signalling grouping channel multiframe structure. .RT .LP .rs .sp 37P .LP [T8.704]\fR .ad r \fBTable 7/G.704 [T8.704], p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 3.2.4.4 \fISignalling grouping channel multiframe alignment signal\fR .sp 9p .RT .PP Bit 3 of the signalling grouping channel, as shown in Table\ 7/G.704, contains the signal grouping channel multiframe alignment signal used to associate the signalling bits in the signal grouping channel with the proper channels of the associated time slot grouping. .PP \fINote\fR \ \(em\ The signalling grouping channel multiframe alignment signal is independent of, and different from, the framing bit of the 1544\ kbit/s frame. .bp .RT .sp 1P .LP 3.2.4.5 \fICRC\(hy6 error detection information for the time slot grouping\fR .sp 9p .RT .PP An optional 2 kbit/s CRC\(hy6 error detection code word may be transmitted in the bit position indicated by CRC\(hy1 through CRC\(hy6 in Table\ 7/G.704. .PP The CRC\(hy6 message block (CMB) is a sequence of 1152 serial bits that is concident with a time slot grouping multiframe. By definition, CMB\ \fIN\fR begins at bit position\ 0 of time slot grouping multiframe\ \fIN\fR and ends at bit position\ 1151 of time slot grouping multiframe\ \fIN\fR . .PP The check\(hybit sequence CRC\(hy1 through CRC\(hy6 transmitted in multiframe \fIN\fR \ +\ 1 is the remainder after multiplication by \fIx\fR \u6\d, and then \fR division (modulo\ 2) by the generator polynomial \fIx\fR \u6\d\ +\ \fIx\fR \ +\ 1 of the the polynomial corresponding to CMB\ \fIN\fR . The first check bit, CRC\(hy1, is the most significant bit of the remainder; the last check bit CRC\(hy6, is the least significant bit. The time slot grouping channel is included in this calculation with bit\ 4 of the time slot grouping channel being set to\ 1. .PP When not utilizing the option to transmit the CRC\(hy6 error detection signal, CRC\(hy1 through CRC\(hy6 shall be set to\ 1. .RT .sp 1P .LP 3.2.4.6 \fISignalling\fR .sp 9p .RT .PP Two alternative methods as given in \(sc\(sc\ 3.2.4.6.1 and 3.2.4.6.2 are recommended. .RT .sp 1P .LP 3.2.4.6.1\ \ \fI .sp 9p .RT .PP Refer to \(sc\ 3.1.3.1. Two successive 32 kbit/s channel time slots are used for 64\ kbit/s common channel signalling transmission. .RT .sp 1P .LP 3.2.4.6.2\ \ \fIChannel associated signalling\fR .sp 9p .RT .PP As indicated in Table 7/G.704, bits 1 and 2 of the signalling grouping channel convey the channel associated signalling information for the channels of the associated time slot grouping. .PP The signalling grouping channel can provide four independent 333\ bit/s signalling channels designated A, B, C and\ D, two independent 667\ bit/s signalling channels designated\ A and\ B, or one 1333\ bit/s signalling channel designated\ A. Where only A\(hyB signalling is used, the A\(hyB signalling is repeated for the C\(hyD positions respectively. Where only A\ signalling is used, the A\ signalling is repeated for the B\(hyC\(hyD positions respectively. .RT .sp 1P .LP 3.2.4.7 \fISignalling grouping channel alarm indication signals\fR .sp 9p .RT .PP As indicated in Table 7/G.704, the signalling grouping channel contains four alarm indication bits, M\fR\d1\u, M\d2\u, M\d3\uand\ M\d4\u. .PP M\d1\uprovides the capability to transmit through the interface a remote time slot grouping alarm indication of a failure in the opposite direction of transmission. .PP M\d2\uprovides the capability to transmit through the interface an indication of a failure in tributary input signals to the network node. .PP M\d3\uprovides the capability to transmit through the interface an indication of a failure in tributary output signals from the network node. .PP M\d4\uis set to 1 whenever M\d1\uand/or M\d2\uand/or M\d3\uare set to\ 1. .RT .sp 1P .LP 3.2.5 \fISignal grouping channel unused bits\fR .sp 9p .RT .PP The bits marked S in Table 7/G.704 are currently unused and set to\ 1. The definition and allocation of the S\(hybits are for further study. .RT .sp 1P .LP 3.2.6 \fILoss and recovery of signalling channel multiframe alignment\fR .sp 9p .RT .PP Loss of the signalling grouping channel multiframe alignment signal is declared when two out of four signalling grouping channel framing bits are in error. The rare occurrence of a single instantaneous slip of \(+- | 1 frames is undetected by the two\(hyout\(hyof\(hyfour algorithm. Signalling grouping channel multiframe alignment shall be declared when the correct sequence of 24\ valid signalling grouping channel framing bits is detected, beginning with the first frame of the multiframe. .bp .RT .sp 1P .LP 3.3 \fIInterface at 1544 kbit/s carrying n \(mu 64 kbit/s\fR .sp 9p .RT .PP Electrical characteristics should follow Recommendation\ G.703. .PP The time slot mapping to the 1544 kbit/s interface is for further study. .RT .LP \fB4\fR \fBCharacteristics of frame structures carrying channels at various bit rates in 6312 kbit/s interfaces\fR .sp 1P .RT .sp 2P .LP 4.1 \fIInterface at 6312 kbit/s carrying 64 kbit/s channels\fR .sp 1P .RT .sp 1P .LP 4.1.1 \fIFrame structure\fR .sp 9p .RT .sp 1P .LP 4.1.1.1 \fINumber of bits per 64 kbit/s channel time slot\fR .sp 9p .RT .PP Eight, numbered 1 to 8. .RT .sp 1P .LP 4.1.1.2 \fINumber of 64 kbit/s channel time slots per frame\fR .sp 9p .RT .PP Bits 1 to 784 in the basic frame carry 98 octet interleaved 64 kbit/s channel time slots, numbered 1\ to\ 98. Five bits per frame ( F\(hybits ) are added at the end of the frame for the frame alignment signal and for other signals. .RT .sp 1P .LP 4.1.1.3 \fIAllocation of the F\(hybits\fR .sp 9p .RT .PP Refer to Table 3/G.704. .RT .sp 1P .LP 4.1.2 \fIUse of 64 kbit/s channel time slots\fR .sp 9p .RT .PP Each 64 kbit/s channel time slot can accomodate e.g., a PCM\(hyencoded voiceband signal conforming to Recommendation\ G.711 or data information with a bit rate up to 64\ kbit/s. 64 kbit/s channel time slots\ 97,\ 98 may be used for signalling. .RT .sp 1P .LP 4.1.3 \fISignalling\fR .sp 9p .RT .PP Two alternative methods as given in \(sc\(sc\ 4.1.3.1 and\ 4.1.3.2 are recommended. .RT .sp 1P .LP 4.1.3.1 \fICommon channel signalling\fR .sp 9p .RT .PP Use of 64 kbit/s channel time slots 97 and 98 for common channel signalling is under study. .RT .sp 1P .LP 4.1.3.2 \fIChannel associated signalling\fR .sp 9p .RT .PP Based on agreement between the Administrations concerned, channel associated signalling is provided for intra\(hyregional circuits according to the following arrangement: .RT .sp 1P .LP 4.1.3.2.1\ \ \fIAllocation of signalling bit\fR .sp 9p .RT .PP Sixteen signalling bits (bit positions 769 to 784) are designated as ST\d1\uto\ ST\d1\\d6\u. One ST\fI\fI\d\fIi\fR\u\(hybit (\fIi\fR \ =\ 1 to\ 16) accomodates signalling information corresponding to six channel time slots \fIi\fR , 16\ +\ \fIi\fR , 32\ +\ \fIi\fR , 48\ +\ \fIi\fR , 64\ +\ \fIi\fR and 80\ +\ \fIi\fR in a manner described in \(sc\ 4.1.3.2.2 below. .RT .sp 1P .LP 4.1.3.2.2\ \ \fISignalling multiframe structure\fR .sp 9p .RT .PP Each ST\(hybit constitutes an independent signalling multiframe over eight frames as shown in Table\ 8/G.704. .bp .RT .LP .rs .sp 32P .LP [T9.704]\fR .ad r \fBTable 8/G.704 [T9.704], p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 4.2 \fIInterfaces at 6312 kbit/s carrying other channels than 64 kbit/s\fR .sp 9p .RT .PP For further study. .RT .LP \fB5\fR \fBCharacteristics of frame structures carrying channels at various bit rates in 2048 kbit/s interfaces\fR .sp 1P .RT .sp 2P .LP 5.1 \fIInterface at 2048 kbit/s carrying 64 kbit/s channels\fR .sp 1P .RT .sp 1P .LP 5.1.1 \fIFrame structure\fR .sp 9p .RT .sp 1P .LP 5.1.1.1 \fINumber of bits per 64 kbit/s channel time slot\fR .sp 9p .RT .PP Eight, numbered 1 to 8. .RT .sp 1P .LP 5.1.1.2 \fINumber of 64 kbit/s channel time slots per frame\fR .sp 9p .RT .PP Bits 1 to 256 in the basic frame carry 32 octet interleaved time slots numbered 0\ to 31. .bp .RT .sp 1P .LP 5.1.1.3 \fIAllocation of the bits of 64 kbit/s channel time slot 0\fR .sp 9p .RT .PP See Table 4a/G.704 (\(sc\ 2.3.2). .RT .sp 1P .LP 5.1.2 \fIUse of other 64 kbit/s channel time slots\fR .sp 9p .RT .PP Each of the 64 kbit/s channel time slots 1 to 15 and 17 to 31 can accomodate e.g., a PCM\(hyencoded voiceband signal according to Recommendation\ G.711 or a 64\ kbit/s digital signal. .PP The 64 kbit/s channel time slot 16 may be used for signalling. If not needed for signalling, in some cases it may be used for a 64\ kbit/s channel in the same way as time slots 1\ to\ 15 and 17\ to\ 31. .RT .sp 1P .LP 5.1.3 \fISignalling\fR .sp 9p .RT .PP The use of 64 kbit/s channel time slot 16 is recommended for either common channel or channel associated signalling as required. .PP The detailed requirements for the organization of particular signalling systems will be included in the specifications for those signalling systems. .RT .sp 1P .LP 5.1.3.1 \fICommon channel signalling\fR .sp 9p .RT .PP The 64 kbit/s channel time slot 16 may be used for common channel signalling systems up to a rate of 64\ kbit/s. The method of obtaining signal alignent will form part of the particular common channel signallling specification. .RT .sp 1P .LP 5.1.3.2 \fIChannel associated signalling\fR .sp 9p .RT .PP This section contains the recommended arrangement for the use of the 64 kbit/s capability of channel time slot\ 16 for channel associated signalling. .RT .sp 1P .LP 5.1.3.2.1\ \ \fIMultiframe structure\fR .sp 9p .RT .PP A multiframe comprises 16 consecutive frames (whose structure is given in \(sc\ 5.1.1 above) and these are numbered from 0 to 15. .PP The multiframe alignment signal is 0000 and occupies digit time slots 1 to 4 of 64\ kbit/s channel time slot 16 in frame\ 0. .RT .sp 1P .LP 5.3.1.2.2\ \ \fIAllocation of 64\(hykbit/s channel time slot 16\fR .sp 9p .RT .PP When 64 kbit/s channel time slot 16 is used for channel associated signalling, the 64\(hykbit/s capacity is sub\(hymultiplexed into lower\(hyrate signalling channels using the multiframe alignement signal as a reference. .PP Details of the bit allocation are given in Table\ 9/G.704. .RT .sp 1P .LP 5.2 \fIInterface at 2048 kbit/s carrying n \(mu 64 kbit/s\fR .sp 9p .RT .PP Electrical characteristics should follow Recommendation G.703 (see Note\ 4 of Preamble to\ G.703). For the accomodation of\ \fIn\fR \ \(mu\ 64\ kbit time slots in the 2048\ kbit/s frame, two situations are envisaged. .RT .sp 1P .LP 5.2.1 \fIOne n \(mu 64 kbit/s signal on the tributary side of a multiplex\fR \fIequipment\fR .sp 9p .RT .PP Time slots of the 2048 kbit/s frame are filled as follows: .RT .LP TS0: according to \(sc\ 2.3; .LP TS16: reserved for the accomodation, if required, of a 64 kbit/s signalling channel. .LP \(em If 2 \(= | fIn\fR \(= | 15, TS1 to TS\fIn\fR are filled with \fIn\fR \ \(mu\ 64 kbit/s data [see\ a) of Figure\ 1/G.704]; .LP \(em If 15 <\ \fIn\fR \(= | 0, TS1 to TS15 and TS17 to TS(\fIn\fR +1) are filled with\ \fIn\fR \ \(mu\ 64\ kbit/s data [see\ b) of Figure\ 1/G.704]. .LP \(em Remaining time slots are filled with all 1s. .bp .LP .rs .sp 20P .LP [T10.704]\fR .ad r \fBTable 9/G.704 [T10.704], p.\fR .sp 1P .RT .ad b .RT .LP .rs .sp 9P .ad r \fBFigure 1/G.704, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 5.2.2 \fIOne or more n \(mu 64 kbit/s signal on the multiplexed signal side\fR \fIof a multiplexing equipment\fR .sp 9p .RT .PP For any one \fIn\fR \ \(mu\ 64 kbit/s signal, time slots of the 2048 kbit/s frame are filled as follows: .RT .LP TS0: according to \(sc\ 2.3; .LP TS16: reserved for the accomodation, if required, of a 64 kbit/s signalling channel. .PP TS(x) of the 2048 kbit/s frame is designated as the time slot into which the first time slot of the\ \fIn\fR \ \(mu\ 64\ kbit/s is accomodated. .LP \(em If \fIx\fR \(= | 5 and \fIx\fR \ +\ (\fIn\fR \(em1) \(= | 5, or, if \fIx\fR \(>=" | 7 and \fIx\fR \ +\ (\fIn\fR \(em1) \(= | 1, then the filling of time slots is from TS | x) to TS | \fIx\fR +\fIn\fR \(em1) [see\ a)and\ b) of Figure\ 2/G.704]; .LP \(em If \fIx\fR \ +\ (\fIn\fR \(em1) \(>=" | 6, then the filling of time slots is from TS | x) to TS15 and TS17 to TS | \fIx\fR +\fIn\fR ) (see\ c) of Figure\ 2/G.704). .PP \fINote\fR \ \(em\ Once \fIn\fR \ \(mu\ 64 kbit/s signal has been accomodated into the multiplexed signal, care should be taken in the interpretation of the above rules to ensure that further such signals only use the time slots which remain spare. .bp .LP .rs .sp 14P .ad r \fBFigure 2/G.704, p.\fR .sp 1P .RT .ad b .RT .LP \fB6\fR \fBCharacteristics of frame structures carrying channels at various bit rates in 8448 kbit/s interface\fR .sp 1P .RT .sp 2P .LP 6.1 \fIInterface at 8448 kbit/s carrying 64 kbit/s channels\fR .sp 1P .RT .sp 1P .LP 6.1.1 \fIFrame structure\fR .sp 9p .RT .sp 1P .LP 6.1.1.1 \fINumber of bits per 64 kbit/s channel time slot\fR .sp 9p .RT .PP Eight, numbered from 1 to 8. .RT .sp 1P .LP 6.1.1.2 \fINumber of 64 kbit/s channel time time slots per frame\fR .sp 9p .RT .PP Bits 1 to 1056 in the basic frame carry 132 octet interleaved 64\ kbit/s channel time slots, numbered form 0\ to 131. .RT .sp 2P .LP 6.1.2 \fIUse of 64 kbit/s channel time slots\fR .sp 1P .RT .sp 1P .LP 6.1.2.1 \fI64 kbit/s channel time slot assignment in case of channel\fR \fIassociated signalling\fR .sp 9p .RT .PP 64 kbit/s channel time slots 5 to 32, 34 to 65, 71 to 98 and 100 to\ 131 are assigned to 120\ telephone channels from 1\ to\ 120. .PP \fR 64 kbit/s channel time slot 0 and the first 6 bits in 64\ kbit/s channel time slot 66 are assigned to framing: the remaining 2\ bits in 64\ kbit/s channel time slot\ 66 are devoted to services. .PP 64 kbit/s channel time slots 67 to 70 are assigned to channel associated signalling as covered in \(sc\ 6.1.4.2 below. .PP 64 kbit/s channel time slots 1 to 4, 33 are left free for national use. .RT .sp 1P .LP 6.1.2.2 \fI64 kbit/s channel time slot assignment in case of common\fR \fIchannel signalling\fR .sp 9p .RT .PP 64 kbit/s channel time slots 2 to 32, 34 to 65, 67 to 98 and\ 100 to\ 131 are available for 127\ telephone, signalling or other service channels. By bilateral agreement between the Administrations concerned, 64\ kbit/s channel time slot\ 1 may either be used to provide another telephone or service channel or left free for service purposes within a digital exchange. .PP The 64 kbit/s channels corresponding to 64\ kbit/s channel time slot\ 1 to\ 32, 34\ to\ 65 (etc.\ as above) are numbered 0\ to\ 127. .bp .PP 64 kbit/s channel time slot 0 and the first 6\ bits in channel time slot\ 66 are assigned to framing, the remaining 2\ bits in 64\ kbit/s channel time slot\ 66 are assigned to service. .PP 64 kbit/s channel time slots 67 to 70 are, in descending order of priority, available for common channel signalling as covered in \(sc\ 6.1.4.1 below. .PP 64 kbit/s channel slot 33 is left free for national use. .RT .sp 1P .LP 6.1.3 \fIDescription of the CRC procedure in 64 kbit/s channel time\fR \fIslot 99\fR .sp 9p .RT .PP In order to provide an end\(hyto\(hyend quality monitoring of the 8\ Mbit/s link, a CRC\(hy6 procedure is used and the six bits\ C\d1\uto\ C\d6\ucomputed at the source location are inserted in bit positions 1\ to\ 6 of the time slot\ 99 (see Figure 3/G.704). .PP In addition, bit 7 of this time slot, denoted E, is used to send in the transmitting direction an indication about the received signal arriving from the opposite direction. Bit\ E indicates whether or not the most recent CRC block arriving at the opposite end had errors. .PP The CRC\(hy6 bits C\d1\uto \d6\uare computed for each frame. The CRC\(hy6 block size is then 132\ octets, i.e.\ 1056\ bits, and the computation is made 8000\ times per second. .RT .LP .rs .sp 5P .ad r \fBFigure 3/G.704, p.\fR .sp 1P .RT .ad b .RT .sp 1P .LP 6.1.3.1 \fIMultiplication/division process\fR .sp 9p .RT .PP A given C\d1\u\(hyC\d6\uword located in frame \fIN\fR is the remainder after multiplication by\ \fIx\fR \u6\d and then division (modulo\ 2) by the generator polynomial\ \fIx\fR \u6\d\ +\ \fIx\fR \ +\ 1 of the polynomial representation of frame (\fIN\fR \(em1). .PP \fINote\fR \ \(em\ When representing the contents of a frame as a polynomial, the first bit in the frame should be taken as being the most significant bit. Similarly C\d1\uis defined to be the most significant bit of the remainder and C\d6\uthe least significant bit of the remainder. .RT .sp 1P .LP 6.1.3.2 \fIEncoding procedure\fR .sp 9p .RT .PP The CRC bit positions are initially set at 0 i.e.: .RT .sp 1P .ce 1000 C\d1\u= C\d2\u= C\d3\u= C\d4\u= C\d5\u= C\d6\u= 0 .ce 0 .sp 1P .PP The frame is then acted upon by the multiplication/division process referred to above in \(sc\ 6.1.3.1. .PP The remainder resulting from the multiplication/division process is stored ready for insertion into the respective CRC locations of the next frame. .PP \fINote\fR \ \(em\ These CRC bits do not affect the computation of the CRC bits in the next frame since the corresponding locations are set to\ 0 before the computation. .RT .sp 1P .LP 6.1.3.3 \fIDecoding procedure\fR .sp 9p .RT .PP A received frame is acted upon by the multiplication/division process, referred to above in \(sc\ 6.1.3.1, after having its CRC bits extracted and replaced by 0s. .PP The remainder resulting from this multiplication/division process is then stored and subsequently compared on a bit by bit basis with the CRC received in the next frame. .PP If the decoder\(hycalculated remainder exactly corresponds to the CRC bits sent from the encoder, it is assumed that the checked frame is error free. .bp .RT .sp 1P .LP 6.1.3.4 \fIAction on\fR \fIbit E\fR .sp 9p .RT .PP Bit E of frame \fIN\fR is set to 1 in the transmitting direction if bits C\d1\uto\ C\d6\udetected in the most recent frame at the opposite end have been found in error (at least one bit in error). If no errors, E\ is set to\ 0. .RT .sp 1P .LP 6.1.4 \fISignalling\fR .sp 9p .RT .PP The use of channel time slots 67 to 70 is recommended for either common channel or channel\(hyassociated signalling as required. The detailed requirements for the organization of particular signalling systems will be included in the specifications for those signalling systems. .RT .sp 1P .LP 6.1.4.1 \fICommon channel signalling\fR .sp 9p .RT .PP 64 kbit/s channel time slots 67 to 70 may be used for common channel signalling in a descending order of priority up to a rate of 64\ kbit/s. The method of obtaining signal alignment will form part of the particular common channel signalling specification. .RT .sp 1P .LP 6.1.4.2 \fIChannel associated signalling\fR .sp 9p .RT .PP The recommended arrangement for the use of the 64 kbit/s capacity in each 64\ kbit/s channel time slot 67\ to\ 70 for channel associated signalling is as follows: .RT .sp 1P .LP 6.1.4.2.1\ \ \fIMultiframe structure\fR .sp 9p .RT .PP A multiframe for each 64 kbit/s bit\(hystream comprises 16 consecutive frames (whose structure is given in \(sc\ 6.1.1 above) and these are numbered from 0\ to\ 15. .PP The multiframe alignment signal is 0000 and occupies digit time slots 1\ to 4\ of channel time slots 67\ to\ 70 in frame\ 0. .RT .sp 1P .LP 6.1.4.2.2\ \ \fIAllocation of 64 kbit/s channel time slots 67 to 70\fR .sp 9p .RT .PP When 64 kbit/s channel time slots 67 to 70 are used for channel associated signalling, the 64\ kbit/s capacity of each of the four 64\ kbit/s channel time slots is sub\(hymultiplexed into lower rate signalling channels using the multiframe alignment signal as a reference. Details of the bit allocation are given in Table\ 10/G.704. .RT .sp 1P .LP 6.2 \fIInterface at 8448 kbit/s carrying other channels than 64 kbit/s\fR .sp 9p .RT .PP For further study. .RT .LP .rs .sp 12P .ad r Blanc .ad b .RT .LP .bp .ce \fBH.T. [T11.704]\fR .ce TABLE\ 10/G.704 .ce \fBBit allocation of 64 kbit/s channel time slots 67 to 70\fR .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; lw(60p) | cw(42p) | cw(42p) | cw(42p) | cw(42p) . { 64 kbit/s channel time slot Frame } 67 68 69 70 _ .T& cw(60p) | cw(42p) | cw(42p) | cw(42p) | cw(42p) . \ 0 0000\fIxyxx\fR 0000\fIxyxx\fR 0000\fIxyxx\fR 0000\fIxyxx\fR .TE .TS center box ; cw(60p) | cw(24p) | cw(18p) | cw(24p) | cw(18p) | cw(24p) | cw(18p) | cw(24p) | cw(18p) . \ 1 \fIabcd\fR Channel 1\ \fIabcd\fR Channel 16 \fIabcd\fR Channel 31 \fIabcd\fR Channel 46 \fIabcd\fR Channel 61 \fIabcd\fR Channel 76 \fIabcd\fR Channel 91 \fIabcd\fR Channel 106 _ . . . . . . . . . . . . . . . . . . _ 15 \fIabcd\fR Channel 15 \fIabcd\fR Channel 30 \fIabcd\fR Channel 45 \fIabcd\fR Channel 60 \fIabcd\fR Channel 75 \fIabcd\fR Channel 90 \fIabcd\fR Channel 105 \fIabcd\fR Channel 120 .TE .LP \fINote\ 1\fR \ \(em\ Channel numbers refer to telephone channel numbers. Refer to \(sc\ 6.1.2.1 for the assignment of 64\ kbit/s channel time slots to the telephone channels. .LP \fINote\ 2\fR \ \(em\ This bit allocation provides four 500\(hybit/s signalling channels designated a, b, c and d for each channel for telephone and other services. With this arrangement, the signalling distortion of each signalling channel introduced by the\ PCM transmission system, will not exceed\ \(+- | \ ms. .LP \fINote\ 3\fR \ \(em\ When bits b, c or d are not used they should have the values: b\ =\ 1, c\ =\ 0, d\ =\ 1. .LP It is recommended the the com bination 0000 of bits \fIa\fR , \fIb\fR , \fIc\fR and \fId\fR should not be used for signalling purposes for channels\ 1\(hy15, 31\(hy45, 61\(hy75 and 91\(hy125. .LP \fINote\ 4\fR \ \(em x = spare bit, to be set to 1 if not used. y = bit used for alarm indication to the remote end. In undisturbed operation, set to\ 0; in an alarm condition, set to\ 1. .nr PS 9 .RT .ad r \fBTableau 10/G.704 [T11.704], p. 14\fR .sp 1P .RT .ad b .RT .LP .sp 5 .ce 1000 ANNEX\ A .ce 0 .ce 1000 (to Recommendation G.704) .sp 9p .RT .ce 0 .ce 1000 \fBExamples of CRC implementations using shift registers\fR .sp 1P .RT .ce 0 .LP A.1 \fICRC\(hy6 procedure for interface at 1544 kbit/s\fR | (Reference: \(sc 2.1.3.1.2) .sp 1P .RT .PP See Figure A\(hy1/G.704. .PP Input I to the shift register: CMB \fIN\fR with F bits set to 1. .PP Generator polynomial of the shift register: \fIx\fR \u6\d\ +\ \fIx\fR \ +\ 1. .bp .RT .LP .rs .sp 6P .ad r \fBFigure A\(hy1/G.704, p.\fR .sp 1P .RT .ad b .RT .PP At I, the CMB is fed serially (i.e.\ bit by bit) into the circuit, starting with bit number\ 1 of the multiframe (see Table\ 1/G.704). When the last bit of the CMB (i.e.\ bit number\ 4632 within the multiframe has been fed into the shift register, the CRC bits \fIe\fR\d1\uto\ \fIe\fR\d6\uare available at the outputs 1\ to\ 6. (Output\ 1 provides the most significant bit, \fIe\fR\d1\u, and output\ 6 the least significant bit, \fIe\fR\d6\u). Bits\ \fIe\fR\d1\uto\ \fIe\fR\d6\uare transmitted in the next CMB (c.f. Table\ 1/G.704). .PP \fINote\fR \ \(em\ The outputs (1 to 6) of the shift register stages are reset to\ 0 after each CMB. .RT .sp 1P .LP A.2 \fICRC\(hy5 procedure for interface at 6312 kbit/s\fR | (Reference: \(sc 2.2.3.2) .sp 9p .RT .PP Input I to the shift register: CMB \fIN\fR . .PP Generator polynomial of the shift register: \fIx\fR \u5\d\ +\ \fIx\fR \u4\d\ +\ \fIx\fR \u2\d\ +\ 1. .RT .LP .rs .sp 6P .ad r \fBFigure A\(hy2/G.704, p.\fR .sp 1P .RT .ad b .RT .PP At I, the CMB is fed serially (i.e.\ bit by bit) into the circuit, starting with bit number\ 1 of frame number\ 1 (see Table\ 3/G.704). When the last bit of the CMB (i.e.\ bit number\ 784 of frame number\ 4) has been fed into the the shift register, the CRC bits \fIe\fR\d1\uto\ \fIe\fR\d5\uare available at the outputs 1\ to\ 5. (Output\ 1 provides the most significant bit, \fIe\fR\d1\u, and output\ 5 the least significant bit, \fIe\fR\d5\u). Bits\ \fIe\fR\d1\uto\ \fIe\fR\d5\uare transmitted in the corresponding multiframe (see Table\ 3/G.704). .PP \fINote\fR \ \(em\ The outputs (1 to 5) of the shift register stages are reset to\ 0 after each CMB. .RT .sp 1P .LP A.3 \fICRC\(hy4 procedure for interface at 2048kbit/s\fR | (Reference: \(sc 2.3.3.5) .sp 9p .RT .PP See Figure A\(hy3/G.704. .PP Input I to the shift register: SMF (\fIN\fR ) with C\d1\u, C\d2\u, C\d3\u, C\d4\uset to\ 0. .PP Generator polynomial of the shift register: \fIx\fR \u4\d\ +\ \fIx\fR \ +\ 1. .RT .LP .rs .sp 6P .ad r \fBFigure A\(hy3/G.704, p.\fR .sp 1P .RT .ad b .RT .PP At I, the SMF is fed serially (i.e.\ bit by bit) into the circuit, starting with bit C\d1\u\ =\ 0 (see Table\ 4b/G.704). When the last bit of the SMF (i.e.\ bit number\ 256 of frame number\ 7, respectively of frame number\ 15) has been fed into the shift register, the CRC bits C\d1\uto\ C\d4\uare available at the outputs 1\ to\ 4. (Output\ 1 provides the most significant bit, C\d1\u, and output\ 4 the least significant bit, C\d4\u). Bits\ C\d1\uto\ C\d4\uare transmitted in the next SMF, i.e.\ SMF(\fIN\fR +1). .PP \fINote\fR \ \(em\ The outputs (1 to 4) of the shift register stages are reset to\ 0 after each SMF. .bp .RT .sp 2P .LP \fBRecommendation\ G.705\fR .RT .sp 2P .ce 1000 \fBCHARACTERISTICS\ REQUIRED\ TO\ \fR \fBTERMINATE\ DIGITAL\fR .EF '% Fascicle\ III.4\ \(em\ Rec.\ G.705'' .OF '''Fascicle\ III.4\ \(em\ Rec.\ G.705 %' .ce 0 .sp 1P .ce 1000 \fBLINKS\ ON\ A\ DIGITAL\ EXCHANGE\fR .ce 0 .sp 1P .ce 1000 \fI(Malaga\(hyTorremolinos, 1984)\fR .sp 9p .RT .ce 0 .sp 1P .PP This Recommendation defines interface conditions and fundamental functions of digital exchange terminal equipments used to terminate digital paths. The multiplex structures are compatible with those described in Recommendation\ G.704, and are applicable to digital paths which connect PCM multiplex equipments to exchanges and to digital paths which interconnect digital exchanges. The locations of these interfaces are described in Recommendations\ Q.502 and\ Q.512 for digital transit and digital local exchanges. .sp 1P .RT .PP The digital exchange terminal is a synchronous equipment which has a frame aligner circuit. In order to meet the network performance objectives of Recommendation\ G.822, the digital exchange terminal should fulfil the synchronization performance as described below. .LP \fB1\fR \fB1544 kbit/s digital path\fR .sp 1P .RT .sp 2P .LP 1.1 \fIGeneral characteristics\fR .sp 1P .RT .sp 1P .LP 1.1.1 \fIBit rate\fR .sp 9p .RT .PP The nominal bit rate is 1544 kbit/s. .PP \fINote\fR \ \(em\ The tolerance on this bit rate should be further studied and specified. .RT .sp 1P .LP 1.1.2 \fITiming signal\fR .sp 9p .RT .PP It should be possible to derive the transmitting timing signal from an external source as specified below. .PP \fINote\fR \ \(em\ For PCM multiplex equipment at the remote end, the timing signal will be derived from the incoming signal at the receive end. .RT .sp 1P .LP 1.1.2.1 \fITiming in a non\(hysynchronized network\fR .sp 9p .RT .PP For a digital exchange the transmitting timing signal will be derived from an office clock. .RT .sp 1P .LP 1.1.2.2 \fITiming in a synchronized network\fR .sp 9p .RT .PP In case of synchronous operation of the network, a network synchronization system will maintain the signal or clocks within agreed timing limits. .RT .sp 1P .LP 1.1.3 \fIInterfaces\fR .sp 9p .RT .PP Refer to \(sc 2 of Recommendation G.703. No interface internal to the switch will be recommended. .RT .sp 1P .LP 1.1.4 \fITransmission performance\fR .sp 9p .RT .PP Transmission performance of the digital path should be the same as that for 1544 kbit/s digital paths between primary PCM multiplex equipment. .RT .sp 1P .LP 1.2 \fIFrame strusture\fR .sp 9p .RT .PP Refer to \(sc 3.1 of Recommendation G.704. .bp .RT .sp 2P .LP 1.3 \fISynchronization performances\fR .sp 1P .RT .sp 1P .LP 1.3.1 \fIWander at the input\fR .sp 9p .RT .PP Refer to \(sc 4 of Recommendation G.824. .RT .sp 1P .LP 1.3.2 \fIJitter at the input\fR .sp 9p .RT .PP Refer to \(sc 4 of Recommendation G.824. .RT .sp 1P .LP 1.3.3 \fIJitter at the output\fR .sp 9p .RT .PP Jitter at the output is under study. .RT .sp 1P .LP 1.3.4 \fISlips\fR .sp 9p .RT .PP Refer to \(sc\(sc 3 and 4 of Recommendation G.822. .RT .sp 1P .LP 1.3.5 \fIForms of frame aligner\fR .sp 9p .RT .PP Refer to \(sc 8 of Recommendation G.811. .RT .LP \fB2\fR \fB6312 kbit/s digital path\fR .sp 1P .RT .sp 2P .LP 2.1 \fIGeneral characteristics\fR .sp 1P .RT .sp 1P .LP 2.1.1 \fIBit rate\fR .sp 9p .RT .PP The nominal bit rate is 6312\ kbit/s. .PP \fINote\fR \ \(em\ The tolerance on this bit rate should be further studied and specified. .RT .sp 1P .LP 2.1.2 \fITiming signal\fR .sp 9p .RT .PP It should be possible to derive the transmitting timing signal from an external source as specified below. .PP \fINote\fR \ \(em\ For PCM multiplex equipment at the remote end, the timing signal will be derived from the incoming signal at the receive end. .RT .sp 1P .LP 2.1.2.1 \fITiming in a non\(hysynchronized network\fR .sp 9p .RT .PP For a digital exchange the transmitting timing signal will be derived from an office clock. .RT .sp 1P .LP 2.1.2.2 \fITiming in a synchronized network\fR .sp 9p .RT .PP In case of synchronous operation of the network, a network synchronization system will maintain the signal or clocks within agreed timing limits. .RT .sp 1P .LP 2.1.3 \fIInterfaces\fR .sp 9p .RT .PP Refer to \(sc\ 3 of Recommendation\ G.703. No interface internal to the switch will be recommended. .RT .sp 1P .LP 2.1.4 \fITransmission performance\fR .sp 9p .RT .PP Transmission performance of the digital path should be the same as that for 6312\ kbit/s digital paths between primary PCM multiplex equipment. .RT .sp 1P .LP 2.2 \fIFrame structure\fR .sp 9p .RT .PP Refer to \(sc\ 3.2 of Recommendation\ G.704. .bp .RT .sp 2P .LP 2.3 \fISynchronization performances\fR .sp 1P .RT .sp 1P .LP 2.3.1 \fIWander at the input\fR .sp 9p .RT .PP Refer to \(sc\ 4 of Recommendation G.824. .RT .sp 1P .LP 2.3.2 \fIJitter at the input\fR .sp 9p .RT .PP Refer to \(sc\ 4 of Recommendation G.824. .RT .sp 1P .LP 2.3.3 \fIJitter at the output\fR .sp 9p .RT .PP Jitter at the output is under study. .RT .sp 1P .LP 2.3.4 \fISlips\fR .sp 9p .RT .PP Refer to \(sc\(sc\ 3 and 4 of Recommendation G.822. .RT .sp 1P .LP 2.3.5 \fIForms of frame aligner\fR .sp 9p .RT .PP Refer to \(sc\ 8 of Recommendation G.811. .RT .LP \fB3\fR \fB2048 kbit/s digital path\fR .sp 1P .RT .sp 2P .LP 3.1 \fIGeneral characteristics\fR .sp 1P .RT .sp 1P .LP 3.1.1 \fIBit rate\fR .sp 9p .RT .PP The nominal bit rate is 2048 kbit/s. This rate will be controlled to within at least \(+- | 0\ parts per million (ppm) at the transmitting end for each direction of transmission. .RT .sp 1P .LP 3.1.2 \fITiming signal\fR .sp 9p .RT .PP The timing signal is a 2048 kHz signal from which the bit rate is derived. .RT .sp 1P .LP 3.1.2.1 \fITiming in a non\(hysynchronized network\fR .sp 9p .RT .PP For a PCM multiplex equipment, the timing signal will be derived from the incoming timing signal at the receive side. For a digital exchange, the transmitting timing signal will be derived from a clock within the digital exchange. .RT .sp 1P .LP 3.1.2.2 \fITiming in a synchronized network\fR .sp 9p .RT .PP In case of synchronous operation of the network, a network synchronization system will maintain the timing signal or clocks within agreed timing limits. .RT .sp 1P .LP 3.1.3 \fIInterfaces\fR .sp 9p .RT .PP Refer to \(sc 6 of Recommendation G.703. No interface, internal to the switch, will be recommended. .RT .sp 1P .LP 3.1.4 \fITransmission performance\fR .sp 9p .RT .PP The transmission performance of the digital path will be the same as that for 2048\ kbit/s digital paths between primary PCM multiplex equipments. .RT .sp 1P .LP 3.2 \fIFrame structure\fR .sp 9p .RT .PP Refer to \(sc 3.3 of Recommendation G.704. .PP Where more signalling capacity is required between exchanges, additional time slots may be utilized for common channel signalling. They should be selected from the slots allocated in PCM multiplexes for data purposes. On routes between exchanges comprising more than one 2048\(hykbit/s digital path, it may be possible to provide an adequate signalling capacity without using time slot\ 16 of all systems on the route. In these circumstances time slot\ 16 in those systems not carrying signalling can be allocated to speech or other services. Time slot\ 0 is reserved for frame alignment, alarms and network synchronization information and should not be used for signalling or speech purposes. .bp .RT .sp 2P .LP 3.3 \fISynchronization performances\fR .sp 1P .RT .sp 1P .LP 3.3.1 \fIWander at the input\fR .sp 9p .RT .PP Refer to \(sc 3 of Recommendation G.823. .RT .sp 1P .LP 3.3.2 \fIJitter at the input\fR .sp 9p .RT .PP Refer to \(sc 3 of Recommendation G.823. .RT .sp 1P .LP 3.3.3 \fIJitter at the output\fR .sp 9p .RT .PP Jitter at the output is under study. .RT .sp 1P .LP 3.3.4 \fISlips\fR .sp 9p .RT .PP Refer to \(sc\(sc 3 and 4 of Recommendation G.822. .RT .sp 1P .LP 3.3.5 \fIForms of frame aligner\fR .sp 9p .RT .PP Refer to \(sc 8 of Recommendation G.811. .RT .LP \fB4\fR \fB8448 kbit/s digital path\fR .sp 1P .RT .sp 2P .LP 4.1 \fIGeneral characteristics\fR .sp 1P .RT .sp 1P .LP 4.1.1 \fIBit rate\fR .sp 9p .RT .PP The nominal bit rate is 8448 kbit/s. This rate will be controlled to within at least \(+- | 0\ parts per million at the transmitting end for each direction of transmission. .RT .sp 1P .LP 4.1.2 \fITiming signal\fR .sp 9p .RT .PP The timing signal is an 8448 kHz signal from which the bit rate is derived. .RT .sp 1P .LP 4.1.2.1 \fITiming in a non\(hysynchronous network\fR .sp 9p .RT .PP For a PCM multiplex equipment, the timing signal will be derived from the incoming timing signal at the receive side. For a digital exchange, the transmitting timing will be derived from a clock within the digital exchange. .RT .sp 1P .LP 4.1.2.2 \fITiming in a synchronous network\fR .sp 9p .RT .PP In case of synchronous operation of the network, a network synchronization system will maintain the timing signal or clocks within agreed timing limits. .RT .sp 1P .LP 4.1.3 \fIInterfaces\fR .sp 9p .RT .PP Refer to \(sc 7 of Recommendation G.703. No interface, internal to the switch, will be recommended. .RT .sp 1P .LP 4.1.4 \fITransmission performance\fR .sp 9p .RT .PP The transmission performance of the digital path will be the same as that for 8448\ kbit/s digital paths between secondary PCM and/or digital multiplex equipments. .RT .sp 1P .LP 4.2 \fIFrame structure\fR .sp 9p .RT .PP Refer to \(sc 3.4 of Recommendation G.704. .PP Where signalling capacity is required between exchanges, time\(hyslots\ 67, 68, 69 and\ 70 may be utilized for common channel signalling in this order of descending priority. Those channels not used for common channel signalling can be used for speech or other purposes. .bp .RT .sp 2P .LP 4.3 \fISynchronization performance\fR .sp 1P .RT .sp 1P .LP 4.3.1 \fIWander at the input\fR .sp 9p .RT .PP Refer to \(sc 3 of Recommendation G.823. .RT .sp 1P .LP 4.3.2 \fIJitter at the input\fR .sp 9p .RT .PP Refer to \(sc 3 of Recommendation G.823. .RT .sp 1P .LP 4.3.3 \fIJitter at the output\fR .sp 9p .RT .PP Jitter at the output is under study. .RT .sp 1P .LP 4.3.4 \fISlips\fR .sp 9p .RT .PP Refer to \(sc\(sc 3 and 4 of Recommendation G.822. .RT .sp 1P .LP 4.3.5 \fIForms of frame aligner\fR .sp 9p .RT .PP Refer to \(sc 8 of Recommendation G.811. \v'1P' .RT .sp 2P .LP \fBRecommendation\ G.706\fR .RT .sp 2P .ce 1000 \fBFRAME ALIGNMENT AND CYCLIC REDUNDANCY CHECK (CRC) PROCEDURES\fR .EF '% Fascicle\ III.4\ \(em\ Rec.\ G.706'' .OF '''Fascicle\ III.4\ \(em\ Rec.\ G.706 %' .ce 0 .sp 1P .ce 1000 \fBRELATING TO BASIC FRAME STRUCTURES DEFINED IN RECOMMENDATION G.704\fR .ce 0 .sp 1P .ce 1000 \fI(Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .LP \fB1\fR \fBGeneral\fR .sp 1P .RT .PP This Recommendation relates to equipment which receives signals with basic frame structures as defined in Recommendation\ G.704. It defines the frame alignment, the cyclic redundancy check (CRC) multiframe alignment and CRC bit error monitoring procedures to be used by such equipment. Annex\ A contains background information about the use of the CRC procedures and their limitations. .RT .sp 2P .LP \fB2\fR \fBFrame alignment and CRC procedures at l544 kbit/s interface\fR .sp 1P .RT .sp 1P .LP 2.1 \fILoss and recovery of frame alignment\fR .sp 9p .RT .PP There are two alternative multiframe structures at the 1544 kbit/s interface: .RT .LP a) 24\(hyframe multiframe, and .LP b) 12\(hyframe multiframe. .sp 1P .LP 2.1.1 \fILoss of frame alignment\fR .sp 9p .RT .PP The frame alignment signal should be monitored to determine if frame alignment has been lost. Loss of frame alignment should be detected within\ 12\ ms. Loss of frame alignment must be confirmed over several frames to avoid the unnecessary initiation of the frame alignment recovery procedure due to transmission bit errors. The frame alignment recovery procedure should commence immediately once loss of frame alignment has been confirmed. .PP \fINote\fR \ \(em\ For the 12\(hyframe multiframe described in Recommendation\ G.704, loss of multiframe alignment is deemed to occur when loss of frame alignment occurs. .bp .RT .sp 2P .LP 2.1.2 \fIRecovery of frame alignment\fR .sp 1P .RT .sp 1P .LP 2.1.2.1 \fIFrame alignment recovery time\fR .sp 9p .RT .PP The frame alignment recovery time is specified in terms of the maximum average reframe time in the absence of errors. The maximum average reframe time is the average time to reframe when the maximum number of bit positions must be examined for locating the frame alignment signal. .RT .LP a) \fI24\(hyframe multiframe\fR .LP The maximum average reframe time should not exceed 15\ ms. .LP \fINote\fR \ \(em\ Some existing designs of equipment were designed to a limit of 50\ ms. .LP b) \fI12\(hyframe multiframe\fR .LP The maximum average reframe time should not exceed 50 ms. .LP \fINote\fR \ \(em\ These times do not include the time required for the CRC procedure for false frame alignment verification defined in \(sc\ 2.2.2. .sp 1P .LP 2.1.2.2 \fIStrategy for frame alignment recovery\fR .sp 9p .RT .LP a) \fI24\(hyframe multiframe\fR .LP Frame alignment should be recovered by detecting the valid frame alignment signal. When the CRC\(hy6 code is utilized for error performance monitoring (see \(sc 2.2.3), the CRC\(hy6 information may be coupled with the framing algorithm to ensure that a valid frame alignment signal contained within the 24\ F\(hybits is the only pattern onto which the reframe circuit can permanently lock. This procedure is illustrated in Figure 1/G.706. .LP b) \fI12\(hyframe multiframe\fR .LP Overall frame alignment should be recovered by way of simultaneous detection of the frame alignment signal and the multiframe alignment signal, or of frame alignment followed by multiframe alignment. .LP .rs .sp 27P .ad r \fBFigure 1/G.706, p. 18\fR .sp 1P .RT .ad b .RT .LP .bp .sp 1P .LP 2.2 \fICRC bit monitoring\fR .sp 9p .RT .PP Error monitoring by CRC\(hy6 assumes a signal quality sufficient for frame alignment to be established so that CRC\(hy6 bits can be correctly accessed. .RT .sp 1P .LP 2.2.1 \fIMonitoring procedure\fR \v'3p' .sp 9p .RT .LP i) A received CRC Message Block (CMB) is acted upon by the multiplicationB/Fdivision process defined in Recommendation\ G.704 after having its F\(hybits replaced by binary\ 1s. .LP ii) The remainder resulting from the division process is then stored and compared on a bit\(hyby\(hybit basis with the CRC bits received in the next CMB. .LP iii) If the remainder exactly corresponds to the CRC bits contained in the next CMB of the received signal, it is assumed that the checked CMB is error\(hyfree. .sp 1P .LP 2.2.2 \fIMonitoring for false frame alignment\fR (see \(sc A.1.1) .sp 9p .RT .PP In the case of the 24\(hyframe multiframe, when the CRC\(hy6 code is utilized for error performance monitoring, it may also be used to provide immunity against spurious frame alignment signals. The procedure described in \(sc\ 2.1.2.2\ a) should be followed. .RT .sp 1P .LP 2.2.3 \fIError performance monitoring using CRC\(hy6\fR (see \(sc A.1.2) .sp 9p .RT .PP For the purpose of error performance monitoring, it should be possible to obtain indications of each CRC message block which is received in error. The consequent error information should be used in accordance with the requirements to be defined in respective equipment Recommendations. .RT .sp 2P .LP \fB3\fR \fBFrame alignment and CRC procedures at 6312 kbitB/Fs interface\fR .sp 1P .RT .sp 1P .LP 3.1 \fILoss and recovery of frame alignment\fR .sp 9p .RT .PP For the 6312 kbitB/Fs hierarchical level, the term \*Qframe alignment\*U is synonymous with \*Qmultiframe alignment\*U. The last five bits of the 789\(hybit frame are designated as the F\(hybits (see Recommendation G.704) and are time\(hyshared as a frame alignment signal and for other purposes. .RT .sp 1P .LP 3.1.1 \fILoss of frame alignment\fR .sp 9p .RT .PP The frame alignment signal should be monitored to determine if frame alignment has been lost. The loss of frame alignment is declared when seven consecutive incorrect frame alignment signals have been received. .PP The recovery of frame alignment procedure should start immediately once loss of frame alignment has been confirmed. .RT .sp 2P .LP 3.1.2 \fIRecovery of frame alignment\fR .sp 1P .RT .sp 1P .LP 3.1.2.1 \fIFrame alignment recovery time\fR .sp 9p .RT .PP The frame alignment recovery time is specified in terms of the maximum average reframe time in the absence of errors. The maximum average reframe time is the average time to reframe when the maximum number of bit positions must be examined for locating the frame alignment signal. .PP The maximum average reframe time should be less than 5\ ms. .RT .sp 1P .LP 3.1.2.2 \fIStrategy for frame alignment recovery\fR .sp 9p .RT .PP Frame alignment should be recovered by detecting three consecutive correct frame alignment signals. In addition to this, the CRC\(hy5 code (see\ \(sc\ 3.2) should be coupled with the framing algorithm to ensure that a valid frame alignment signal contained within the F\(hybits is the only pattern onto which the reframe circuit can permanently lock. This procedure is illustrated in Figure 1/G.706. .bp .RT .sp 1P .LP 3.2 \fICRC bit monitoring\fR .sp 9p .RT .PP Error monitoring by CRC\(hy5 assumes a signal quality sufficient for frame alignment to be established so that the CRC\(hy5 bits can be correctly accessed. .RT .sp 1P .LP 3.2.1 \fIMonitoring procedure\fR \v'3p' .sp 9p .RT .LP i) A received sequence of 3156 serial bits (i.e. 3151 bits of CMB and 5 CRC bits) is divided by the generator polynomial defined in Recommendation G.704. .LP ii) If the remainder resulting from the division process is 00000, it is assumed that the checked CMB is error\(hyfree. .sp 1P .LP 3.2.2 \fIMonitoring for false frame alignment\fR (see \(sc A.1.1) .sp 9p .RT .PP The procedure in \(sc 3.1.2.2 should be followed when the CRC\(hy5 code is used to provide immunity against false frame alignment signal. .PP Using the CRC\(hy5 code, it should be possible to detect false frame alignment within 1 second and with greater than 0.99 probability. On detection of such an event, a re\(hysearch for correct frame alignment should be initiated. .PP With a random error ratio of 10\uD\dlF261\u4\d, the mean time between two events of falsely initiating a search for frame alignment due to an excessive number of errored CRC message blocks should be more than one year. .PP \fINote\ 1\fR \ \(em\ With a random error ratio of approximately 10\uD\dlF261\u3\d, it is almost impossible to distinguish whether CRC errors are caused by the false frame alignment or by transmission bit errors. .PP \fINote\ 2\fR \ \(em\ To achieve the probability bounds stated above, one method is to count the errored CRC\(hy5 message blocks with the understanding that a count of 32 consecutive errored CRC\(hy5 blocks indicates false frame alignment. .RT .sp 1P .LP 3.2.3 \fIError performance monitoring using CRC\(hy5\fR (see \(sc A.1.2) .sp 9p .RT .PP For the purpose of error performance monitoring, it should be possible to obtain indications for each CRC message block which is received in error. The consequent error information should be used in accordance with the requirements to be defined in the respective equipment Recommendations. .RT .LP \fB4\fR \fBFrame alignment and CRC procedures at 2048 kbit/s interface\fR .sp 1P .RT .sp 2P .LP 4.1 \fILoss and recovery of frame alignment\fR .sp 1P .RT .sp 1P .LP 4.1.1 \fILoss of frame alignment\fR .sp 9p .RT .PP Frame alignment will be assumed to have been lost when three consecutive incorrect frame alignment signals have been received. .PP \fINote\ 1\fR \ \(em\ In addition to the preceding, in order to limit the effect of spurious frame alignment signals, the following procedure may be used: .RT .LP Frame alignment will be assumed to have been lost when bit\ 2 in time slot\ 0 in frames not containing the frame alignment signal has been received with an error on three consecutive occasions. .PP \fINote\ 2\fR \ \(em\ Loss of frame alignment can also be invoked by an inability to achieve CRC multiframe alignment in accordance with\ \(sc\ 4.2, or by exceeding a specified count of errored CRC message blocks as indicated in \(sc\ 4.3.2. .sp 1P .LP 4.1.2 \fIStrategy for frame alignment recovery\fR .sp 9p .RT .PP Frame alignment will be assumed to have been recovered when the following sequence is detected: .RT .LP \(em for the first time, the presence of the correct frame alignment signal; .LP \(em the absence of the frame alignment signal in the following frame detected by verifying that bit 2 of the basic frame is a\ 1; .LP \(em for the second time, the presence of the correct frame alignment signal in the next frame. .bp .PP \fINote\fR \ \(em\ To avoid the possibility of a state in which no frame alignment can be achieved due to the presence of a spurious frame alignment signal, the following procedure may be used: .LP When a valid frame alignment signal is detected in frame \fIn\fR , a check should be made to ensure that a frame alignment signal does not exist in frame \fIn\fR \ +\ 1, and also that a frame alignment signal exists in frame \fIn\fR + 2. Failure to meet one or both of these requirements should cause a new search to be initiated in frame \fIn\fR + 2. .sp 1P .LP 4.2 \fICRC multiframe alignment using information in bit\ 1 of the\fR \fIbasic frame\fR .sp 9p .RT .PP If a condition of assumed frame alignment has been achieved, CRC multiframe alignment should be deemed to have occurred if at least two valid CRC multiframe alignment signals can be located within 8 ms, the time separating two CRC multiframe alignment signals being 2 ms or a multiple of 2 ms. The search for the CRC multiframe alignment signal should be made only in basic frames not containing the frame alignment signal. .PP If multiframe alignment cannot be achieved within\ 8\ ms, it should be assumed that frame alignment is due to a spurious frame alignment signal and a re\(hysearch for frame alignment should be initiated. .PP \fINote\ 1\fR \ \(em\ The re\(hysearch for frame alignment should be started at a point just after the location of the assumed spurious frame alignment signal. This will usually avoid realignment onto the spurious frame alignment signal. .PP \fINote\ 2\fR \ \(em\ Consequent actions taken as a result of loss of frame alignment should no longer be applied once frame alignment has been recovered. However, if CRC multiframe alignment cannot be achieved within a time limit in the range of 100\ ms to 500 ms, e.g. owing to the CRC procedure not being implemented at the transmitting side, consequent actions should be taken equivalent to those specified for loss of frame alignment. .RT .sp 1P .LP 4.3 \fICRC bit monitoring\fR .sp 9p .RT .PP If frame and CRC multiframe alignment have been achieved, the monitoring of the CRC bits in each sub\(hymultiframe should commence. .RT .sp 1P .LP 4.3.1 \fIMonitoring procedure\fR \v'3p' .sp 9p .RT .LP i) A received CRC sub\(hymultiframe (SMF) is acted upon by the multiplication/division process defined in Recommendation\ G.704 after having its CRC bits extracted and replaced by\ 0s. .LP ii) The remainder resulting from the division process is then stored and subsequently compared on a bit\(hyby\(hybit basis with the CRC bits received in the next SMF. .LP iii) If the remainder exactly corresponds to the CRC bits contained in the next SMF of the received signal, it is assumed that the checked SMF is error\(hyfree. .sp 1P .LP 4.3.2 \fIMonitoring for false frame alignment\fR (see \(sc A.1.1) .sp 9p .RT .PP It should be possible to detect a condition of false frame alignment within 1 second and with a probability greater than 0.99. On detection of such an event, a re\(hysearch for frame alignment should be initiated. .PP With a random error ratio of 10\uD\dlF261\u3\d the probability of falsely initiating a search for frame alignment due to an excessive number of errored CRC blocks should be less than 10\uD\dlF261\u4\d over a\ 1 second period. .PP Figure 2/G.706 shows an illustration of the procedure to be followed in passing from the frame alignment search to error monitoring using CRC. .PP \fINote\ 1\fR \ \(em\ The re\(hysearch for frame alignment should be started at a point just after the location of the assumed spurious frame alignment signal. This will usually avoid realignment onto the spurious frame alignment signal. .PP \fINote\ 2\fR \ \(em\ To achieve the probability bounds stated above, a preferred threshold count is 915 errored CRC blocks out of 1000, with the understanding that a count of \(>=" | 15 errored CRC blocks indicates false frame alignment. .bp .RT .LP .rs .sp 38P .ad r \fBFigure 2/G.706, p. \fR .sp 1P .RT .ad b .RT .sp 1P .LP 4.3.3 \fIError performance monitoring using CRC\(hy4\fR (see \(sc A.1.2) .sp 9p .RT .PP Information on the status of the CRC processing should be made available in two forms: .RT .LP a) \fIDirect information\fR .LP Every time a CRC block is detected in error, it will be necessary to indicate this condition. .LP b) \fIIntegrated information\fR .LP In consecutive 1 second periods, the number of errored CRC blocks should be made available. This number will be in the range 0 to 1000 (decimal). .sp 2P .LP \fB5\fR \fBFrame alignment and CRC procedures at 8448 kbitB/Fs interface\fR .sp 1P .RT .PP For further study. .bp .RT .ce 1000 ANNEX A .ce 0 .ce 1000 (to Recommendation G.706) .sp 9p .RT .ce 0 .ce 1000 \fBBackground information on the use of cyclic\fR .sp 1P .RT .ce 0 .ce 1000 \fBredundancy check (CRC) procedures\fR .ce 0 .LP A.1 \fIReasons for application of CRC\fR .sp 1P .RT .PP CRC procedures can be used for both protection against false frame alignment and for bit error monitoring. .RT .sp 1P .LP A.1.1 \fIProtection against false frame alignment\fR .sp 9p .RT .PP The CRC procedures are used to protect against false frame alignment of receivers of multiplex signals. For example, false frame alignment could occur in an ISDN if a user imitates a frame alignment signal in his non\(hyvoice terminal. However, since a user is not controlling the composition of a multiplex frame, the addition of CRC bits, and evaluation of these bits in the receiver, leads to detection of the false frame alignment. .RT .sp 1P .LP A.1.2 \fIBit error monitoring\fR .sp 9p .RT .PP The CRC procedure is also used for improved bit error ratio monitoring if low values of error ratio (e.g. 10\uD\dlF261\u6\d) are to be considered. CRC monitoring (like monitoring of the frame alignment signal) takes account of the entire digital link between the source and sink of a multiplex signal, as opposed to code violation monitoring (e.g. monitoring of AMI, HDB3 or B8ZS violations) which concerns only the digital line section nearest to the receiver, or in many cases only an interface line [e.g. between a digital multiplexer and an Exchange Terminal (ET)]. .RT .sp 2P .LP A.2 \fILimitations of CRC procedures\fR .sp 1P .RT .sp 1P .LP A.2.1 \fIProbability of undetected bit errors\fR .sp 9p .RT .PP It can be estimated [1] that for CRC\(hy\fIn\fR , and long message/check blocks, the probability that an error remains undetected approaches 2\uD\dlF261\fI\fI \u\fIn\fR\deven with a high bit error ratio; with a low bit error ratio, the probability is lower. The resulting inaccuracy (at most, with CRC\(hy4, about 6% of blocks with undetected errors; similarly, with CRC\(hy6, 1.6%) is tolerable for the required purpose. .RT .sp 1P .LP A.2.2 \fILimitation of application to bit error ratio measurement\fR .sp 9p .RT .PP The CRC monitoring procedure is not well suited to measure values of bit error ratio that are so high that on average every message/check block contains at least one bit error (i.e. for BER = 10\uD\dlF261\u3\d or higher). .RT .sp 2P .LP \fBReference\fR .sp 1P .RT .LP [1] LEUNG, C. and WITZKE, K.A. \(em A comparison of some error detecting CRC code standards. \fIIEEE Trans\fR . Vol. COM\(hy33, pp. 996\(hy998, 1985. .sp 2P .LP \fBRecommendation G.707\fR .RT .sp 2P .sp 1P .ce 1000 \fBSYNCHRONOUS DIGITAL HIERARCHY BIT RATES\fR .EF '% Fascicle\ III.4\ \(em\ Rec.\ G.707'' .OF '''Fascicle\ III.4\ \(em\ Rec.\ G.707 %' .ce 0 .sp 1P .ce 1000 \fI(Melbourne, 1988)\fR .sp 9p .RT .ce 0 .sp 1P .LP The CCITT, .sp 1P .RT .sp 1P .LP \fIconsidering\fR .sp 9p .RT .PP (a) that Recommendation G.702 specifies a number of digital hierarchy bit rates for 1544 kbitB/Fs and 2048 kbit/s based digital networks; .PP (b) that the various hierarchy levels specified in Recommendation\ G.702 are interconnected by means of digital multiplexing employing justification methods; .bp .PP (c) that synchronous digital multiplexing and a related synchronous digital hierarchy offer advantages such as: .LP \(em simplified multiplexingB/Fdemultiplexing techniques; .LP \(em direct access to lower speed tributaries, without need to multiplexB/Fdemultiplex the entire high speed signal; .LP \(em enhanced Operations, Administration and Maintenance (OAM) capabilities; .LP \(em easy growth to higher bit rates in step with the evolution of transmission technology; .PP (d) that the synchronous digital hierarchy rates need to be chosen such that they allow the transport of digital signals: .LP \(em at hierarchical bit rates as specified in Recommendation G.702; .LP \(em at broadband channel bit rates; .PP (e) that Recommendation G.708 specifies the Network Node Interface (NNI) for the synchronous digital hierarchy; .PP ( f ) that Recommendation G.709 specifies the synchronous multiplexing structure; .PP (g) that Recommendations G.707, G.708 and G.709 form a coherent set of specifications for the synchronous digital hierarchy and NNI. .sp 1P .LP \fIrecommends\fR .sp 9p .RT .PP (1) that the first level of the synchronous digital hierarchy shall be 155 | 20 kbit/s; .PP (2) that higher synchronous digital hierarchy bit rates shall be obtained as integer multiples of the first level bit rate; .PP (3) that higher synchronous digital hierachy levels should be denoted by the corresponding multiplication factor of the first level rate; .PP (4) that the following bit rates should constitute the synchronous digital hierarchy: .LP .sp 2 .ce \fBH.T. [T1.707]\fR .ce TABLE\ 1/G.707 .ps 9 .vs 11 .nr VS 11 .nr PS 9 .TS center box; cw(72p) | cw(72p) . { Synchronous digital hierarchy level } Hierarchical bit rate kbit/s _ .T& cw(72p) | cw(72p) . 1 155 | 20 _ .T& cw(72p) | cw(72p) . 4 622 | 80 .TE .LP \fINote\fR \ \(em\ The specification of higher synchronous digital hierarchy levels requires further study. Possible candidates are: .TS cw(36p) | lw(90p) . \fILevel\fR \fIBit rate\fR .T& cw(36p) | lw(90p) . \ 8 12 16 { 1 | 44 | 60 kbit/s 1 | 66 | 40 kbit/s 2 | 88 | 20 kbit/s } .TE .nr PS 9 .RT .ad r \fBTableau 1/G.707 [T1.707], p. 20\fR .sp 1P .RT .ad b .RT .LP .rs .sp 2P .ad r Blanc .ad b .RT .LP .bp